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Sat, 24 Oct 2026 00:37:06 +0000 Message-ID: <3e107248-d0aa-4c5d-9c51-d5b73be003e6@intel.com> Date: Fri, 23 Oct 2026 17:37:04 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 05/12] x86/resctrl: Attach ACPI ERDT information to L3 mon domain on CPU online From: Reinette Chatre To: Chen Yu , CC: , , , , , , , , , , , Hongyu Ning References: <2d3327d86480b1a41bf1a7c935317f14884a83f9.1791933001.git.yu.c.chen@intel.com> <2317c664-0c9b-4dad-b135-a771959be024@intel.com> Content-Language: en-US In-Reply-To: <2317c664-0c9b-4dad-b135-a771959be024@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MW4PR04CA0105.namprd04.prod.outlook.com (2603:10b6:303:83::20) To SJ2PR11MB8370.namprd11.prod.outlook.com (2603:10b6:a03:540::20) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR11MB8370:EE_|FT1PR11MB671131:EE_ X-MS-Office365-Filtering-Correlation-Id: a7f813ff-cdaf-4b9a-8fd8-08df3166ee18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|23010399003|11063799006|4143699003|56012099006|261021121427099003|261022075727099003|261022105027099003|261009223027099003|10067099003|22082099003|18002099003|6133799003|3023799007; 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Unless it is something really simple, which > this is not, there has to be some context before the change is described. > >> >> ERDT and CPUID enumerate CPU-to-L3-domain membership independently: CPUID leaf 4 >> describes the L3 cache topology, while the firmware CACD sub-table lists the >> CPUs of each ERDT domain. Both views must agree on a CPU's L3 domain for that >> CPU to be monitored safely. >> >> When a CPU comes online, validate that firmware and CPUID agree on its L3 domain >> and bind the CPU to its ERDT domain before adding it to any resctrl domain. > > "bind the CPU to its ERDT domain" is this not what patch #3 did? > > "adding it" - what does "it" refer to? the ERDT domain or the CPU? > >> Fail the CPU online operation on a mismatch for now. Leaving the CPU >> online but outside all resctrl domains is doable, but it would require a >> change to cpus_ctrl_write() to reject CPUs that are online but not tracked by >> any resctrl group. The current approach is stricter, but simpler. > > I do not believe failing the CPU online operation is actually possible. > > resctrl_arch_late_init() is a late initcall and all boot CPUs are already online, > so the failure during this time will result in resctrl not being initialized at > all without impacting online CPUs. A CPU onlined after that will fail to > initialize, but that will make the CPU unusable for *everything*, not just > unmonitored. This sounds extreme for an ERDT table issue that should never happen. > > A CPU that is online is still able to run tasks and the earlier enumeration > ensured that MSR_IA32_PQR_ASSOC is accessible and what the valid values for it > are. Even this "failure" path demonstrates this by calling clear_closid_rmid() > that writes to MSR_IA32_PQR_ASSOC *after* the supposed failure. > > resctrl's current behavior when a CPU cannot be onlined, for example when > domain creation fails, is to *not* prevent CPU from onlining. If a domain > cannot be created then the CPU is still added to the default group's > CPU mask (resctrl_online_cpu()) to ensure that tasks can continue to > be scheduled on it by writing to MSR_IA32_PQR_ASSOC with values known to > be valid. > > Such a CPU is *not* added to a domain's CPU mask so resctrl will not > attempt to make any configuration changes to it or read any counters from it. > correction: with the CMT event marked as "any_cpu" it may be possible for the counter to be read from a CPU that was not added to the domain, but this read will go to MMIO that should succeed? At this point the system will already be in a state with the logs showing "Firmware Bug" so further attempts at using resctrl cannot be expected to be ideal. The CPU should continue to be usable otherwise. Reinette