Re: [PATCH v3 1/5] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>]

On 9/10/2026 3:33 PM, Krzysztof Kozlowski wrote:
> On Wed, Sep 09, 2026 at 05:18:16PM +0530, Krishna Chaitanya Chundru wrote:
>> +  vdda-phy-a-supply: true
>> +
>> +  vdda-phy-b-supply: true
>> +
>> +  vdda-phy-c-supply: true
>> +
>> +  vdda-phy-d-supply: true
>> +
>> +  vdda-pll-a-supply: true
>> +
>> +  vdda-pll-b-supply: true
>> +
>> +  vdda-pll-c-supply: true
>> +
>> +  vdda-pll-d-supply: true
>> +
>> +  qcom,link-mode:
>> +    description: |
>> +      Reference to the TCSR syscon and the offset of the
>> +      TCSR_PCIE_LINK_CONFIG_MODE register.
>> +        0 (QMP_PCIE_NORD_MODE_X16)        — all ports ganged as x16
>> +        1 (QMP_PCIE_NORD_MODE_X8_X8)      — x8 (port A) + x8 (port B+C+D)
>> +        2 (QMP_PCIE_NORD_MODE_X8_X4_X4)   — x8 (A) + x4 (B) + x4 (C+D)
>> +        3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2)— x8 (A) + x4 (B) + x2 (C) + x2 (D)
> What does this mean? The phy working mode is defined by phy-cells
> argument, so what are these numbers above?
I wasn't clear on the description of phy-cells properly, we need phy-cells to
be 1, so
that controller nodes can reference phy with index indicating which port of
phy being used.

I will update the description in next series.

The TCSR register is the real value programmed by TZ to tell which mode we are
currently
operating.

- Krishna Chaitanya.
>
> Best regards,
> Krzysztof
>