From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB00844AB9D; Mon, 7 Sep 2026 09:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788773394; cv=none; b=GR6rrjIoIt/Mfnle/YkcmnTn4avlJOebV+otuG2w5HdiDN+z6KaUkiRChenp0sy9JMzwbydiexop4SwgrZBfDVAAkL/ldfzwlFgolpgzDX7NzU9SldixxFrjcdZdxxzVMD+FqpOgQ4IlOt31ZXDIgxz9BcFmla2AuvI71+1DT7s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788773394; c=relaxed/simple; bh=5281dcRb8zZBtkO1oJ2CF7fGdlascRV7BzcJZfe5OMY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=gG1fh0Ib+/FPbl13m4DTTnono+DP4Ga0giY1YIXVYC3cxvDQtbj4rzkFD7uxUTTv4ss57M0S4EhUzniSoaHfHjJUWeJ3QVhABzi1jXXsupXUqBN0eGgz/D4xkcAR0BQJ8rY5sYCuPurqout75ZUlw6D+oaF2eAqStlwjaXEE1fo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WG07sVej; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WG07sVej" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93EA71F00A3A; Mon, 7 Sep 2026 09:29:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788773383; bh=VtCPek+5saPOvgRgewn8SWkbjVqNPiUS7tnHPudCp4k=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=WG07sVejUwJBWxiPp6B0tTO6fiAH3aigLFdHESjaqBD9fprnpQcls8Cv8a40AXQQq m0x4DjMVboYHhrA0Ipot+Tiv9/YUtur3mC2LmWZ+wf7ERZSD2b70teFoaDkSYP7RJf XGX1+5BtouWCDLv2f1pjMYSITTYBzE2VGcGnSchmsVtO9/TzLdpTNOPygLoQEeH0QC rj8Ws6zxjLGJ1QG+5p6JF3lwkjCrgz+s5t8IYqO3F0h3UwO7sMhJbrYr1NNtrPCT3p RI5d0hnje7C705jblZjzG8L7X2HC0NQNHC3GkWT4QM5llNWdQEdlQTr/Zd6Ys3bNYk TcPehRvRpC0Nw== Message-ID: <3e619085-3311-4acd-9493-e849875563d7@kernel.org> Date: Mon, 7 Sep 2026 10:29:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] dt-bindings: media: qcom,glymur-camss: Add Glymur CAMSS To: Nihal Kumar Gupta , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Lee Jones , Guru Das Srinagesh , Liam Girdwood , Mark Brown Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mfd@lists.linux.dev, Suresh Vankadara , Vikram Sharma References: <20260907-glymur_camss-v2-0-75f7982dc983@oss.qualcomm.com> <20260907-glymur_camss-v2-2-75f7982dc983@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; keydata= xsFNBGRJNSgBEADD7Vm2ZFa+v+JGJ2QYTJqQAkqis/uOHkhdFNXqpBarVBd47QU/DMNU5Rxg jedMQEmHoeDbJ6UOpjbrUQ63c5sgG1JbroHJJctwsEI75OOlekMuebEbjIJBLfgENGwPBMHv piv5TgCWr0VgYaXfp2eh2LINFywzqj823HiDPibQAXDrjzvF1ogksi/6cQZs8d4if8YQkLOr YISFouG+eR0nN1I7mUfIddXOWu6lJeTyqbWVurv58k2ekIXKaOC9ixLHFbcfYV0hOgRaTwQC B8CYF9nfqZla19iItfsN9QxN+ZdQjcRoYipp6HPCMfJlKH7GfaFcW93LKc4DKJ2lVL+pg/OQ lythZbjRPY492NG9kZ65aYstCs90uhMUEVVPuGUw7wBEku+6IEwZfrbMVKeWzLlPyM4Hv9hM 8ktxSmxWsPTPqpBC8eyeAQLalMELAyVcZlkaCtEcbj7w4l/JkYz+4l37obG8ZD+B34udBUUz MsAJ8foDFrBh2MOFA3hxD6G90D23mmWsri7pnKA2tZs92aQX7Ee+FbCyg6g5ln62Sq83ZDbf 53DdBs55EVpBadeInWmXhzCHPQx06H+CwTEjShTYIaMmBfrewvYUDKvFTC5iKQhAEUgt6i94 JsbG7NoeqcxkUMcBOEUQ3uCQG1D70ugspgXc0wd3Rimiq6535wARAQABzSFCcnlhbiBPJ0Rv bm9naHVlIDxib2RAa2VybmVsLm9yZz7CwZEEEwEIADsWIQTmk/sqq6Nt4Rerb7QicTuzoY3I OgUCZ+R+mwIbAwULCQgHAgIiAgYVCgkICwIEFgIDAQIeBwIXgAAKCRAicTuzoY3IOimUD/94 BwVEJX31JRe2sxbB/e1w2p8x1bxvTw5AeIzpV3ox7coJg1bSU2mnGuj1V4o0Yxf/3zmcJzCN VfVjwRF8Ii3GnC7uUXk2t+87piQfKTyJAYQABhZUKgoVJbjJq/S+C3XCKIyBA+EiezoUsgsA jTzwU+FzV7zVWIXFPJNtBERLwboE9w9U3KjAExOa1kSY8eLrsg6kOwlOHWy5UsQqYOjrS96M mzm2xuc1+RCjrndAyYhCnrOKvJ67HsPnBeJCjw7ImGD/U1GchwYbX8o3DO3JNHm3qfC86ZqX 2sCouENg4OzgPTtLKUrueM6xsu6KMM7gj17vxsiR3KQEoJnnMB8D1xtBofN3mFZE0wD9M24m 8yGunZbtntMCUHzIrlJgAPwKWKuGOYtA8UgMTFkccnUJtQrg9KotKtEF/FuftG9zLG9XEkt4 5ZdNgbSoLWgelu3T47mbOJ8LHhiLaCWP7yrovtVAvLUQ1BsiA42u8ECrFCFvQj9nrejE/ICv kP+uqcKtdDvP9HrIGycF1WZyfZLp0RvopKW92FLvI4I1QFWJ+wenk6+LGyJ5bzlrWzevjxmf nHcXE6sJBHrE7eijlbbImDAi3uLYN8Nd9Dm11IDAy4GAIQxSiQn0yblDhPiyGtchy80EVkCm g9k17Wol+2E2mC4DKgVdCkyUtTRSLgsJCs7BTQRkSTUoARAAuTnmWHBS6izRcEE93ajpzI7h dgQO4U3IRvOEsvIKR5NGcNEs0ngGebwsZ/lVULjN4vYU0LleqVhPBidNXUoZCN3A0F0Z2Ov8 NZdef+2EhQPBVWxFO7JBzhe8Z3ALj+wFtlg8akJjBzU56azW/iJzAobqHVrudzKoO2b1/CMg VbiAQ+RXjgfN5kY/HqYDU7mw+hXuUV9PbtX1L8xqQQac95oM9rHzKHHpiVwxTeJnGQsa+THi Kze+YET3rCoGHMvOQEJhdrucTv5FpAakKdkOFNel9FFckLRKEuWgCzhpFsjQ7xbirQgFUxG9 vlk1+q4hMRGNyEqoD6svYEeqbiUSd0oPUJeioiC3rNMRCNHLVrfZ2J6SCPkxfda08uzSdDQU 1/YPjOh8ZtQDMu7WctZ3XO288Z1gyBR49V7fbFs2w4sQxG+h/enlxqP7fdw1mjUlZjU5huCJ ielS0oEaIpmUpkugli7x4WhwLnhK2EbSoz7nLBC0y+ALUOdMlz/Y1l9xRt+bkDhpmf4O4IcI MxgZ0QMLq8rHDkGaEbsgZZHQPS58T0XE3IP30Q9SNxsruCMXtd2hYtBssf/wohc6JVsTtMg2 VYTPDPIFNZFSXupEJB7jlqpDWJ8ooJfJRLBatbjT5+mVQaMYB7Hs/t+zWYWaJKHyc8O6WLEC NUV5Tdt5EkkAEQEAAcLBdgQYAQoAIBYhBOaT+yqro23hF6tvtCJxO7Ohjcg6BQJkSTUoAhsM AAoJECJxO7Ohjcg6LuIQALnXt36OUuK43wqw6UYt0cnN6EbUqJHApAF5eNFn0jCCB2XELjSz JKJwuNAweowBdabiBniJ+501WIW+ewEsz1uby5fUQjZuCEsIkuaIluyfUFPb73qrQyAGuusd 7teA4WT+/jUku9g7lX5sVoRCrKQPkd16f6Bzfztyqyjcn43/X5yQI+wlboQ6HuKe/3I3yiOx OgmCHzOawpC9PvhEcKj79RLM3Zz5Ts5AuHpRX70Jz8Be76LwVFLp5Msx3S24ZTU1lBo2uiJ3 xSkay2lTpyVWRPx9vgcwzxGguOPJQJwsQeLb7wpoJMPpD3ERoaRii7Q7hvmxklpZjhKYWB3d t6nQ497Ek9loCrp3MIjRCSDN5xEGffiHks9yTeGMUQwO4tX8RE04uOJPkUY7uCFzFqN6/qey X3oFfPgkULMdiHofPAL1OskZSTzGPSfTYRE46NCJw8yoZBQ/oOyWeqaUQbK0wmW/g81wm8p7 LKSGEglMpiX07M1AotgvylN5C8fjbouoK+/RAMsXkk8jba6rPfuuXPaDjCyyKn6zSVHETnHW 3AJbgVY50T8STpnxayBQvWbCvu+6NOEjXCbyaOJig+5l0zlGN9XHjdANXC5HnwmyaGRL9YDq Jh2nVXVJDincOdQRdKcJjYLqaOAoWrYWSDi1iZGspHBTDrnOvfMQzzHY In-Reply-To: <20260907-glymur_camss-v2-2-75f7982dc983@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 07/09/2026 09:13, Nihal Kumar Gupta wrote: > X1E80100 supports both the legacy CSIPHY resources and the new PHY API; > Glymur uses only the new PHY API via standalone phy@ child nodes, > so per-CSIPHY clocks, interrupts and supplies are absent here. What's up with the commit log here ? There is no legacy CSIPHY in this.. ? > > X1E80100 has four CSIPHY instances while Glymur has three > (CSIPHY0, CSIPHY1, CSIPHY4), expressed entirely in DT. > > Co-developed-by: Vikram Sharma > Signed-off-by: Vikram Sharma > Signed-off-by: Nihal Kumar Gupta > --- > .../bindings/media/qcom,glymur-camss.yaml | 300 +++++++++++++++++++++ > 1 file changed, 300 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-camss.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-camss.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..a0b77edc212319fad69113f3d55ca24f184d4b23 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,glymur-camss.yaml > @@ -0,0 +1,300 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,glymur-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Glymur Camera Subsystem (CAMSS) > + > +maintainers: > + - Nihal Kumar Gupta > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,glymur-camss > + > + reg: > + maxItems: 13 > + > + reg-names: > + items: > + - const: csid_wrapper > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csitpg0 > + - const: csitpg1 > + - const: csitpg2 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + clocks: > + maxItems: 20 > + > + clock-names: > + items: > + - const: camnoc_nrt_axi > + - const: camnoc_rt_axi > + - const: core_ahb > + - const: cpas_ahb > + - const: cpas_fast_ahb > + - const: cpas_vfe0 > + - const: cpas_vfe1 > + - const: cpas_vfe_lite > + - const: csid > + - const: csid_csiphy_rx > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe1 > + - const: vfe1_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 9 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + interconnects: > + maxItems: 4 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_mnoc > + - const: sf_mnoc > + - const: sf_icp_mnoc > + > + iommus: > + items: > + - description: S1 HLOS IFE and IFE_LITE non-protected > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + patternProperties: > + "^port@[0-3]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interrupts > + - interrupt-names > + - interconnects > + - interconnect-names > + - iommus > + - power-domains > + - power-domain-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: isp@acb6000 { > + compatible = "qcom,glymur-camss"; > + > + reg = <0x0 0x0acb6000 0x0 0x1000>, > + <0x0 0x0acb7000 0x0 0x2000>, > + <0x0 0x0acb9000 0x0 0x2000>, > + <0x0 0x0acbb000 0x0 0x2000>, > + <0x0 0x0acc6000 0x0 0x1000>, > + <0x0 0x0acca000 0x0 0x1000>, > + <0x0 0x0acf6000 0x0 0x1000>, > + <0x0 0x0acf7000 0x0 0x1000>, > + <0x0 0x0acf8000 0x0 0x1000>, > + <0x0 0x0ac62000 0x0 0xf000>, > + <0x0 0x0ac71000 0x0 0xf000>, > + <0x0 0x0acc7000 0x0 0x2000>, > + <0x0 0x0accb000 0x0 0x2000>; > + reg-names = "csid_wrapper", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csitpg0", > + "csitpg1", > + "csitpg2", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + clock-names = "camnoc_nrt_axi", > + "camnoc_rt_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe_lite", > + "csid", > + "csid_csiphy_rx", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ahb", > + "hf_mnoc", > + "sf_mnoc", > + "sf_icp_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x20>; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", > + "ife1", > + "top"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + camss_csiphy0_ep: endpoint { > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&csiphy0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + camss_csiphy1_ep: endpoint { > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&csiphy1_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + camss_csiphy4_ep: endpoint { > + data-lanes = <1 2 3 4>; > + remote-endpoint = <&csiphy4_out>; > + }; > + }; > + }; > + }; > + }; > > -- > 2.34.1 > >