From: Yang Shi <yang@os.amperecomputing.com>
To: James Morse <james.morse@arm.com>,
jgg@ziepe.ca, nicolinc@nvidia.com, will@kernel.org,
robin.murphy@arm.com
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for AmpereOne
Date: Wed, 2 Oct 2024 10:39:36 -0700 [thread overview]
Message-ID: <3e772c30-d7b0-409c-83f1-5fc5a961567e@os.amperecomputing.com> (raw)
In-Reply-To: <d4b53bbb-333a-45b9-9eb0-23ddd0820a14@arm.com>
On 10/2/24 9:58 AM, James Morse wrote:
> Hello!
>
> On 01/10/2024 19:03, Yang Shi wrote:
>> The commit ce410410f1a7 ("iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx()")
>> calculated the last index of L1 stream table by 1 << smmu->sid_bits. 1
>> is 32 bit value.
>> However AmpereOne has 32-bit stream id size. This resulted in
>> ouf-of-bound shift. The disassembly of shift is:
>>
>> ldr w2, [x19, 828] //, smmu_7(D)->sid_bits
>> mov w20, 1
>> lsl w20, w20, w2
>>
>> According to ARM spec, if the registers are 32 bit, the instruction actually
>> does:
>> dest = src << (shift % 32)
>>
>> So it actually shifted by zero bit.
>>
>> This caused v6.12-rc1 failed to boot on AmpereOne
> Same here - one of arm's reference designs prints 1 giga-tonne of:
> | arm-smmu-v3 arm-smmu-v3.5.auto: event 0x02 received:
> | arm-smmu-v3 arm-smmu-v3.5.auto: 0x0000c90000000002
> | arm-smmu-v3 arm-smmu-v3.5.auto: 0x0000000000000000
> | arm-smmu-v3 arm-smmu-v3.5.auto: 0x0000000000000000
> | arm-smmu-v3 arm-smmu-v3.5.auto: 0x0000000000000000
>
> during boot - then fails to find the nvme.
> Bisect points to ce410410f1a7, and the below diff fixes it.
>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> index 737c5b882355..01a2faee04bc 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> @@ -3625,7 +3625,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
>> u32 l1size;
>> struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
>> unsigned int last_sid_idx =
>> - arm_smmu_strtab_l1_idx((1 << smmu->sid_bits) - 1);
>> + arm_smmu_strtab_l1_idx((1UL << smmu->sid_bits) - 1);
>>
>> /* Calculate the L1 size, capped to the SIDSIZE. */
>> cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES);
>
> Tested-by: James Morse <james.morse@arm.com>
Thank you for testing. I will change the patch subject a little bit to
make it more general.
>
>
> Thanks,
>
> James
prev parent reply other threads:[~2024-10-02 17:39 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 18:03 Yang Shi
2024-10-01 18:27 ` Nicolin Chen
2024-10-01 19:09 ` Yang Shi
2024-10-01 19:18 ` Jason Gunthorpe
2024-10-01 19:38 ` Yang Shi
2024-10-01 19:46 ` Jason Gunthorpe
2024-10-01 20:31 ` Yang Shi
2024-10-01 20:47 ` Yang Shi
2024-10-01 21:02 ` Jason Gunthorpe
2024-10-01 21:32 ` Yang Shi
2024-10-02 16:58 ` James Morse
2024-10-01 19:29 ` Nicolin Chen
2024-10-01 19:48 ` Yang Shi
2024-10-02 9:59 ` Robin Murphy
2024-10-02 15:38 ` Yang Shi
2024-10-02 16:58 ` James Morse
2024-10-02 17:39 ` Yang Shi [this message]
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