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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0def2esm2146839666b.61.2025.08.12.02.55.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 02:55:54 -0700 (PDT) Message-ID: <3e790d99-5c6c-4148-85f5-0023a621afeb@oss.qualcomm.com> Date: Tue, 12 Aug 2025 11:55:52 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read() To: Gabor Juhos , Mark Brown Cc: Md Sadre Alam , Varadarajan Narayanan , Sricharan Ramabadhran , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=G6EcE8k5 c=1 sm=1 tr=0 ts=689b0fad cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=pGLkceISAAAA:8 a=5qz9QPgusZpkEaXBDdAA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfX1kvgQmvlvlY0 0iGKnzhMQ1Ii5MtzTYDXl84abF4LbND3yWZQZBgNAzVVLGDE2iiGYAurNktJlHyN7G0nEVD4LBa nYu1q/9QZ8IG4tAMOXk0SszO45TDqQ+dne7NMcyz+m4C1TcmjSEGkbbEOfN1Wrg5Z6UXZal5fg0 ehdO+LB4Q1jYo/Hag3bOyaUfjH/jiPysymt4rm1ZKY+DvSIVO87vZ2L4X9zCluZ+ZIlvlBECkDu 57aJ4P448qetoh7kwCk8i8fRkaD19k+hxYkuW+XQ/xIEqGEnFqzcEkd1k8vEOqzuPMS9Qks/UpU vutOLXw1MsRDfgv5ymZI1W6rJFZ0Iu7ZUruMsM6KATj7Ib/p1qqiO+2xQ7LSDrntxHBa37duXQw jpemLGoZ X-Proofpoint-ORIG-GUID: lA1HONkqWTb1ymjyuU8MB56OQbz9gQeZ X-Proofpoint-GUID: lA1HONkqWTb1ymjyuU8MB56OQbz9gQeZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 On 8/8/25 7:15 PM, Gabor Juhos wrote: > During raw read, neither the status of the ECC correction nor the erased > state of the codeword gets checked by the qcom_spi_read_cw_raw() function, > so in case of raw access reading the corresponding registers via DMA is > superfluous. > > Extend the qcom_spi_config_cw_read() function to evaluate the existing > (but actually unused) 'use_ecc' parameter, and configure reading only > the flash status register when ECC is not used. > > With the change, the code gets in line with the corresponding part of > the config_nand_cw_read() function in the qcom_nandc driver. > > Signed-off-by: Gabor Juhos > --- > drivers/spi/spi-qpic-snand.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c > index 7b76d2c82a5287df13ee6fcebc4abbe58ca861ee..119003c4784890458a41c67fa8bc17d721030b0d 100644 > --- a/drivers/spi/spi-qpic-snand.c > +++ b/drivers/spi/spi-qpic-snand.c > @@ -494,9 +494,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int c > qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); > qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); > > - qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); > - qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, > - NAND_BAM_NEXT_SGL); > + if (use_ecc) { > + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); Why are we reading 2 registers (the 2 in the func call) here, but 1 everywhere else? Konrad > + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, > + NAND_BAM_NEXT_SGL); > + } else { > + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, > + NAND_BAM_NEXT_SGL); > + } > } > > static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) > > --- > base-commit: 13d0fe84a214658254a7412b2b46ec1507dc51f0 > change-id: 20250805-qpic-snand-handle-use_ecc-de929376d50b > > Best regards,