From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ECD6331EB7; Wed, 23 Sep 2026 07:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790147912; cv=none; b=E8ED9xpnVjp20R6oUt3bI7EPkQszJg6eRqi1nNOgJ0niAEwbQWonUhphzud14j/9cDM8Uo+CY4Za4ChzQqFR9RGLDXyl+5zNlP9xevFmCrCpJNeReiCZ8s3PzkV8zziHf4ydU9/aA9R6g6pne2zey/RLxtHbC80vtoLtO+IspnA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790147912; c=relaxed/simple; bh=0Lwr0/tWfAZ9fseMLREPGQiGCFcJK1ojgMrbwR3LwYQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=pgingF27wn7RckGQR+0MgvGpo4WUjpOjwGBM1AmMNd4y0+LorEVCCfEV3XMn81Qv+7p+BIgib3OGQ39bkAxwQvvuBRVYKO73t5oFpUADKiOsPc+oZazXJlF1LT3SfrUG31M65DEfrZfRNl5shPG5o0JQtalqdV4TAUWv3zZvGNE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AgkSvpyD; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AgkSvpyD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AF641F000FF; Wed, 23 Sep 2026 07:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790147910; bh=hjeJPL69ZDqze5/p8wzcHo2cRaykHOUG+cZBY+I4Ow0=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=AgkSvpyD0aEFsFPDzirqDI2fo1fs2XImrxaomjofc/LRjrWC7t9UBBSkPB8jWEh5X 7N6KYfapuHMAxfSwq8VQ26WiONDxjWxTZyQplaeIOqlvYZ4+z/bLdsA2iYvRU/hznx O/N0fLnrRShxrG1yjA1JaeXrUdIeEK/0gh+01GWGv6alJVJr3BRjN1PqAUNqmOb7Bu vNZY5ZePju1uxu/ZDZauTaYLekKVN9oszqIlEP1osNsmCqsoiC7mwibS3tXXh80lT4 njSnS/Osa13TXMIkxVEww1OUlL4oA4V1m7U3sdmTiL/aQtfrPS/cYZIWDwJQAUSMMH /7cfWpmXkVPOQ== Message-ID: <3e7b66be-124a-446f-bdfd-b0fe30fff796@kernel.org> Date: Wed, 23 Sep 2026 09:18:24 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml To: Alex Elder Cc: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260918165234.687224-1-elder@riscstar.com> <20260918165234.687224-3-elder@riscstar.com> <20260920-messy-successful-caracara-fcdbcd@quoll> <1ac16236-284a-4d01-b68a-4b32d5c5287c@riscstar.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/09/2026 15:13, Alex Elder wrote: > On 9/20/26 1:21 PM, Krzysztof Kozlowski wrote: >>> diff --git a/include/dt-bindings/clock/toshiba,tc9564.h b/include/dt-bindings/clock/toshiba,tc9564.h >>> new file mode 100644 >>> index 0000000000000..75732fddd3025 >>> --- /dev/null >>> +++ b/include/dt-bindings/clock/toshiba,tc9564.h >>> @@ -0,0 +1,54 @@ >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >>> + >>> +/* >>> + * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved. >>> + */ >>> + >>> +#ifndef __ClOCK_TOSHIBA_TC9564_H__ >>> +#define __ClOCK_TOSHIBA_TC9564_H__ >>> + >>> +/* Clock IDs */ >>> + >>> +#define CLOCK_MCU 0 >>> +#define CLOCK_INTC 1 >>> +/* #define CLOCK_PCIE 2 */ >>> +/* #define CLOCK_I2C 3 */ >> Drop both, and SRAM is number 2. Or enable and implement them. > > I forgot to respond to this. I think you are confused. > > SRAM is BAR number 2. This is defining clock IDs. > > And the reason these are commented out is that, while they > do exist, we explicitly do not want anyone to disable either > of these clocks because PCIe uses them. This clock (and > reset) control is accessed via PCIe. > > I do accept that someone might want me to simply omit > these commented-out definitions, and I'd be fine with > that. > > But your suggestion wasn't sensible so I wanted to clear > that up before deleting these. > Indices should be continuous, there is no point in having holes in numbering. Best regards, Krzysztof