Re: [PATCH v2 08/17] clk: imx: imx8mp: fix clock tree update of TF-A managed clocks

[Ahmad Fatoum <a.fatoum@pengutronix.de>]

Hello Peng,

The commit message looks eerily familiar ;)
Small correction below.

On 10.05.24 11:19, Peng Fan (OSS) wrote:
> From: Zhipeng Wang <zhipeng.wang_1@nxp.com>
> 
> On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
> for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
> SiP and then does clk_set_parent on the DDR muxes to synchronize
> the clock tree.
> 
> since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"),
> these TF-A managed muxes have SET_PARENT_GATE set, which results
> in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
> 
> clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c)
> 
> This is safe to do, because updating the Linux clock tree to reflect
> reality will always be glitch-free.

This refers to the next sentence, thus swap position of this sentence
with the next one:

> 
> commit 926bf91248dd
> ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this
> method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it.
s/this method/imx8m_clk_hw_fw_managed_composite which sets the SET_PARENT_GATE flag/

> 
> Another reason to this patch is that powersave image BT music
> requires dram to be 400MTS, so clk_set_parent(dram_alt_src,
> sys1_pll_800m); is required. Without this patch, it will not succeed.
> 
> Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
> Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

With commit message adjusted:

Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

Thanks,
Ahmad

> ---
>  drivers/clk/imx/clk-imx8mp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 670aa2bab301..e561ff7b135f 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -551,8 +551,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  
>  	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
>  
> -	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
> -	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
> +	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
> +	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
>  	hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
>  	hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
>  	hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
> 

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