From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADAF63AF66E for ; Mon, 10 Aug 2026 10:51:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786359068; cv=none; b=WS9Hp/TgRZZlbF1YxKyJySWTdJkjq7svvagPE8Mc+N+Fnry3WwB7/LMGrSBjPBYpe0zy11kZrxAcEoTJj4W3F7MqiJHURkl3/nFywAbLJ6NAIrasN9P1XuuLASi7HB7MuvbivtBB4gRDjXm6mmo7EThRZx6Kjokrn+zNQ38ysnI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786359068; c=relaxed/simple; bh=OdvPnCB6xQlHVlyGm0ohiIvtRQb0SYoo74LFotI5rN0=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=FdIXylS60RG7oZmVbRDytQcn13R4xXFUGPGD8flXvmhwQR8qAVLWg8ixvAZ1zn6rmb/LX6lv9OS8kWfl3jWaaDf6Gu+XgJrcqDKtpFxuInYGxrdOfQDq1oDp3lSUUuo+pJ+jlrBpvYBUpQ2Xuj3udfeeJcLi/Drv6kfL8rM5UQ4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Egi7YfR9; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Egi7YfR9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D27EB1F000E9; Mon, 10 Aug 2026 10:51:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786359066; bh=xLHS6YFJTedplV4n7LxqLwFMrxkB1+znfaGp/bxa3zc=; h=Date:Subject:To:References:From:In-Reply-To; b=Egi7YfR93y5YSw1O5izsmblKRVW39dcLBDcA3vTCT7//3W80p4jybvSYOAbXy4C8i +rn4yLyohvV7q2dYdgjt/jovxufnsQqeuF/vx9vKs/XJUenN7dfmG7r2uaujhaJYJ5 LfWLbyQ9kwHRHPjuFD9rfgI0DeSpfeaPeNCC8y4k4Y98sr8tSu0Ia9Isa3BbqPCSh+ hrXS9zh1R5KDimG62qUHxp5pTX37iZvA/TqDGVMUC35GsKRuNkHinrv67Nb7N3+8Tp ypn+K9mMzWYsbmWr7OyZWXWRiaXPIVuK6//8zschqF+WU1hRLvoqSTGlfBD9HA26z1 7xOR7N2twlCtA== Message-ID: <3ecf4107-f7e8-4c72-87f6-9ca52ee10e7d@kernel.org> Date: Mon, 10 Aug 2026 12:51:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: defconfig: Enable QMP PCIe Multi-PHY driver To: Qiang Yu , linux-kernel@vger.kernel.org References: <20260807-enable_multiphy_0807-v1-1-142f911d356a@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 07/08/2026 14:50, Qiang Yu wrote: > This driver supports PHYs shared across multiple PCIe controllers, e.g. > the PCIe3 PHY block on Glymur that PCIe3a and PCIe3b both use. Enable it What is Glymur? Srsly, same questions all over again. Every second defconfig change from Qualcomm. > so those platforms keep working with this defconfig. Drop, pointless. > > Signed-off-by: Qiang Yu > --- > This patch depends on below patch series: > Link: https://lore.kernel.org/all/20260807-glymur_linkmode_0807-v9-0-dd1c7e236e29@oss.qualcomm.com/ Why? Above patchset targets SoC tree, so why this does not? Why it is not part of that patchset, why none of maintainers are CC-ed here? > --- Best regards, Krzysztof