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Fri, 21 Apr 2023 22:05:41 GMT Received: from [10.110.0.180] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 21 Apr 2023 15:05:40 -0700 Message-ID: <3ee67248-c94c-5f3d-527e-914e8c8b4a31@quicinc.com> Date: Fri, 21 Apr 2023 15:05:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v1 5/5] drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets Content-Language: en-US To: Dmitry Baryshkov , , , , , , , , , , CC: Abhinav Kumar , , , , , References: <1682033114-28483-1-git-send-email-quic_khsieh@quicinc.com> <1682033114-28483-6-git-send-email-quic_khsieh@quicinc.com> From: Kuogee Hsieh In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oCjwfEqMgOxWu08l3yMN7gwYqwWBmTMi X-Proofpoint-ORIG-GUID: oCjwfEqMgOxWu08l3yMN7gwYqwWBmTMi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-21_08,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=940 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304210193 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/20/2023 5:07 PM, Dmitry Baryshkov wrote: > On 21/04/2023 02:25, Kuogee Hsieh wrote: >> From: Abhinav Kumar >> >> Add DSC 1.2 hardware blocks to the catalog with necessary >> sub-block and feature flag information. >> Each display compression engine (DCE) contains dual hard >> slice DSC encoders so both share same base address but with >> its own different sub block address. > > Please correct line wrapping. 72-75 is usually the preferred width > >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Kuogee Hsieh >> --- >>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h  | 19 >> +++++++++++++++++++ >>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h  | 11 +++++++++++ >>   .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h    | 21 >> +++++++++++++++++++++ >>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h  | 19 >> +++++++++++++++++++ >>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h  | 19 >> +++++++++++++++++++ >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c      | 12 ++++++++++-- >>   6 files changed, 99 insertions(+), 2 deletions(-) >> > > > [I commented on sm8550, it applies to all the rest of platforms] > >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> index 9e40303..72a7bcf 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> @@ -165,6 +165,23 @@ static const struct dpu_merge_3d_cfg >> sm8550_merge_3d[] = { >>       MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), >>   }; >>   +static const struct dpu_dsc_sub_blks sm8550_dsc_sblk_0 = { >> +    .enc = {.base = 0x100, .len = 0x100}, >> +    .ctl = {.base = 0xF00, .len = 0x10}, >> +}; >> + >> +static const struct dpu_dsc_sub_blks sm8550_dsc_sblk_1 = { >> +    .enc = {.base = 0x200, .len = 0x100}, >> +    .ctl = {.base = 0xF80, .len = 0x10}, >> +}; > > Please keep sblk in dpu_hw_catalog for now. > >> + >> +static const struct dpu_dsc_cfg sm8550_dsc[] = { >> +    DSC_BLK_1_2("dsc_0", DSC_0, 0x80000, 0x100, 0, sm8550_dsc_sblk_0), >> +    DSC_BLK_1_2("dsc_0", DSC_1, 0x80000, 0x100, 0, sm8550_dsc_sblk_1), > > Is there a reason why index in "dsc_N" doesn't match the DSC_n which > comes next to it? usually each DCE (display compression engine) contains two hard slice encoders. DSC_0 and DSC_1 (index) is belong to dsc_0. If there are two DCE, then DSC_2 and DSC_3 belong to dsc_1 > >> +    DSC_BLK_1_2("dsc_1", DSC_2, 0x81000, 0x100, >> BIT(DPU_DSC_NATIVE_422_EN), sm8550_dsc_sblk_0), >> +    DSC_BLK_1_2("dsc_1", DSC_3, 0x81000, 0x100, >> BIT(DPU_DSC_NATIVE_422_EN), sm8550_dsc_sblk_1), >> +}; >> + >>   static const struct dpu_intf_cfg sm8550_intf[] = { >>       INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, >> MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >>       /* TODO TE sub-blocks for intf1 & intf2 */ >> @@ -218,6 +235,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { >>       .dspp = sm8550_dspp, >>       .pingpong_count = ARRAY_SIZE(sm8550_pp), >>       .pingpong = sm8550_pp, >> +    .dsc = sm8550_dsc, >> +    .dsc_count = ARRAY_SIZE(sm8550_dsc), >>       .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), >>       .merge_3d = sm8550_merge_3d, >>       .intf_count = ARRAY_SIZE(sm8550_intf), >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 03f162a..be08158 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -1,6 +1,6 @@ >>   // SPDX-License-Identifier: GPL-2.0-only >>   /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. >> - * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights >> reserved. >> + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All >> rights reserved. >>    */ >>     #define pr_fmt(fmt)    "[drm:%s:%d] " fmt, __func__, __LINE__ >> @@ -540,7 +540,15 @@ static const struct dpu_pingpong_sub_blks >> sc7280_pp_sblk = { >>       {\ >>       .name = _name, .id = _id, \ >>       .base = _base, .len = 0x140, \ >> -    .features = _features, \ >> +    .features = BIT(DPU_DSC_HW_REV_1_1) | _features, \ >> +    } >> + >> +#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \ >> +    {\ >> +    .name = _name, .id = _id, \ >> +    .base = _base, .len = _len, \ >> +    .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \ >> +    .sblk = &_sblk, \ >>       } >> /************************************************************* >