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From: Jinjie Ruan <ruanjinjie@huawei.com>
To: Will Deacon <will@kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, Thomas Gleixner <tglx@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Borislav Petkov <bp@alien8.de>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	David Woodhouse <dwmw@amazon.co.uk>,
	Peter Zijlstra <peterz@infradead.org>,
	Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH 16/19] arm64: cpu_ops: Expose optional argument to target cpu in ->cpu_boot()
Date: Tue, 8 Sep 2026 20:12:51 +0800	[thread overview]
Message-ID: <3f18b449-390a-4611-8bcd-a3b60e37056d@huawei.com> (raw)
In-Reply-To: <20260907164024.17164-17-will@kernel.org>



在 2026/9/8 0:40, Will Deacon 写道:
> Some backend implementations of 'struct cpu_ops', notably PSCI v0.2+,
> allow an optional argument to be passed in register X0 to the target
> CPU during boot.
> 
> Expose this functionality by extending the ->cpu_boot() CPU operation
> to take an additional argument which is ignored unless the new optional
> ->cpu_boot_has_arg() callback is present and returns 'true'. For now,
> we continue to pass zero.
> 
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/include/asm/cpu_ops.h          |  6 +++++-
>  arch/arm64/kernel/acpi_parking_protocol.c |  3 ++-
>  arch/arm64/kernel/psci.c                  | 11 +++++++++--
>  arch/arm64/kernel/smp.c                   |  2 +-
>  arch/arm64/kernel/smp_spin_table.c        |  2 +-
>  5 files changed, 18 insertions(+), 6 deletions(-)

Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>

> 
> diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
> index cd298a8710d8..e7662a1879d9 100644
> --- a/arch/arm64/include/asm/cpu_ops.h
> +++ b/arch/arm64/include/asm/cpu_ops.h
> @@ -21,6 +21,9 @@
>   *		mechanism for doing so, tests whether it is possible to boot
>   *		the given CPU.
>   * @cpu_boot:	Boots a cpu into the kernel.
> + * @cpu_boot_has_arg: Optionally determines whether @cpu_boot passes its
> + *		      (non-zero) second argument to the booting CPU in
> + *		      register x0.
>   * @cpu_postboot: Optionally, perform any post-boot cleanup or necessary
>   *		synchronisation. Called from the cpu being booted.
>   * @cpu_can_disable: Determines whether a CPU can be disabled based on
> @@ -36,7 +39,8 @@ struct cpu_operations {
>  	const char	*name;
>  	int		(*cpu_init)(unsigned int);
>  	int		(*cpu_prepare)(unsigned int);
> -	int		(*cpu_boot)(unsigned int);
> +	int		(*cpu_boot)(unsigned int, unsigned long);
> +	bool		(*cpu_boot_has_arg)(void);
>  	void		(*cpu_postboot)(void);
>  #ifdef CONFIG_HOTPLUG_CPU
>  	bool		(*cpu_can_disable)(unsigned int cpu);
> diff --git a/arch/arm64/kernel/acpi_parking_protocol.c b/arch/arm64/kernel/acpi_parking_protocol.c
> index e1be29e608b7..24ebde1241bf 100644
> --- a/arch/arm64/kernel/acpi_parking_protocol.c
> +++ b/arch/arm64/kernel/acpi_parking_protocol.c
> @@ -56,7 +56,8 @@ static int acpi_parking_protocol_cpu_prepare(unsigned int cpu)
>  	return 0;
>  }
>  
> -static int acpi_parking_protocol_cpu_boot(unsigned int cpu)
> +static int acpi_parking_protocol_cpu_boot(unsigned int cpu,
> +					  unsigned long ignored)
>  {
>  	struct cpu_mailbox_entry *cpu_entry = &cpu_mailbox_entries[cpu];
>  	struct parking_protocol_mailbox __iomem *mailbox;
> diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
> index 6b25a12ed143..3ba4fa14b9e3 100644
> --- a/arch/arm64/kernel/psci.c
> +++ b/arch/arm64/kernel/psci.c
> @@ -36,16 +36,22 @@ static int __init cpu_psci_cpu_prepare(unsigned int cpu)
>  	return 0;
>  }
>  
> -static int cpu_psci_cpu_boot(unsigned int cpu)
> +static int cpu_psci_cpu_boot(unsigned int cpu, unsigned long context)
>  {
>  	phys_addr_t pa_secondary_entry = __pa_symbol(secondary_entry);
> -	int err = psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry, 0);
> +	int err = psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry,
> +				  context);
>  	if (err && err != -EPERM)
>  		pr_err("failed to boot CPU%d (%d)\n", cpu, err);
>  
>  	return err;
>  }
>  
> +static bool cpu_psci_cpu_boot_has_context(void)
> +{
> +	return psci_ops.get_version() >= PSCI_VERSION(0, 2);
> +}
> +
>  #ifdef CONFIG_HOTPLUG_CPU
>  static bool cpu_psci_cpu_can_disable(unsigned int cpu)
>  {
> @@ -114,6 +120,7 @@ const struct cpu_operations cpu_psci_ops = {
>  	.cpu_init	= cpu_psci_cpu_init,
>  	.cpu_prepare	= cpu_psci_cpu_prepare,
>  	.cpu_boot	= cpu_psci_cpu_boot,
> +	.cpu_boot_has_arg = cpu_psci_cpu_boot_has_context,
>  #ifdef CONFIG_HOTPLUG_CPU
>  	.cpu_can_disable = cpu_psci_cpu_can_disable,
>  	.cpu_disable	= cpu_psci_cpu_disable,
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 2e98a92eb764..b57f8f752f78 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -103,7 +103,7 @@ static int boot_secondary(unsigned int cpu, struct task_struct *idle)
>  	const struct cpu_operations *ops = get_secondary_cpu_ops();
>  
>  	if (ops->cpu_boot)
> -		return ops->cpu_boot(cpu);
> +		return ops->cpu_boot(cpu, 0);
>  
>  	return -EOPNOTSUPP;
>  }
> diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c
> index 49029eace3ad..a5e6f444c25f 100644
> --- a/arch/arm64/kernel/smp_spin_table.c
> +++ b/arch/arm64/kernel/smp_spin_table.c
> @@ -104,7 +104,7 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu)
>  	return 0;
>  }
>  
> -static int smp_spin_table_cpu_boot(unsigned int cpu)
> +static int smp_spin_table_cpu_boot(unsigned int cpu, unsigned long ignored)
>  {
>  	/*
>  	 * Update the pen release flag.


  reply	other threads:[~2026-09-08 12:12 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-07 16:40 [PATCH 00/19] arm64: Implement parallel CPU onlining with PSCI v0.2+ Will Deacon
2026-09-07 16:40 ` [PATCH 01/19] cpu/hotplug: Clean up cmpxchg() logic in cpuhp_can_boot_ap() Will Deacon
2026-09-08  2:55   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 02/19] cpu/hotplug: Avoid trying to bring up CPUs that are already online Will Deacon
2026-09-08  3:13   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 03/19] cpu/hotplug: Avoid busy-polling on archs where cpu_relax() is a no-op Will Deacon
2026-09-08  4:00   ` Jinjie Ruan
2026-09-11  7:16   ` Jinjie Ruan
2026-09-11 12:57     ` Will Deacon
2026-09-16  1:15       ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 04/19] cpu/hotplug: Propagate bring-up status to arch_cpuhp_cleanup_kick_cpu() Will Deacon
2026-09-08  4:05   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 05/19] arm64: smp: Tidy up smp_prepare_cpus() Will Deacon
2026-09-08  7:35   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 06/19] arm64: smp: Tidy up cpuinfo init and cpufeature updates Will Deacon
2026-09-08  7:53   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 07/19] arm64: smp: Defer update of secondary CPU capabilities Will Deacon
2026-09-08  8:20   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 08/19] arm64: smp: Don't bother printing the I-cache policy for each CPU Will Deacon
2026-09-08  8:33   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 09/19] arm64: smp: Defer RCU registration during secondary CPU bringup Will Deacon
2026-09-08  8:55   ` Jinjie Ruan
2026-09-08 10:19     ` Will Deacon
2026-09-08 11:25       ` Jinjie Ruan
2026-09-09 12:36         ` Will Deacon
2026-09-10  2:47           ` Jinjie Ruan
2026-09-11 12:52             ` Will Deacon
2026-09-16  2:40               ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 10/19] arm64: smp: Use generic HOTPLUG_CORE_SYNC_FULL machinery for CPU onlining Will Deacon
2026-09-08  9:01   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 11/19] arm64: smp: Use generic HOTPLUG_SPLIT_STARTUP " Will Deacon
2026-09-08  9:10   ` Jinjie Ruan
2026-09-08 11:35   ` Jinjie Ruan
2026-09-11 12:55     ` Will Deacon
2026-09-07 16:40 ` [PATCH 12/19] arm64: cpu_ops: Make 'cpu_operations' pointer global instead of per-cpu Will Deacon
2026-09-08 11:32   ` Jinjie Ruan
2026-09-11 12:55     ` Will Deacon
2026-09-16  1:12       ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 13/19] arm64: cpu_ops: Introduce get_secondary_cpu_ops() Will Deacon
2026-09-08 11:56   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 14/19] firmware/psci: Cache PSCI v0.2+ version number to avoid redundant SMCs Will Deacon
2026-09-08 11:57   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 15/19] firmware/psci: Extend ->cpu_on() callback to take an additional argument Will Deacon
2026-09-08 12:05   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 16/19] arm64: cpu_ops: Expose optional argument to target cpu in ->cpu_boot() Will Deacon
2026-09-08 12:12   ` Jinjie Ruan [this message]
2026-09-07 16:40 ` [PATCH 17/19] arm64: smp: Pass secondary CPU boot parameters via firmware if possible Will Deacon
2026-09-08 12:16   ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 18/19] arm64: smp: Use generic HOTPLUG_PARALLEL machinery for CPU onlining Will Deacon
2026-09-08 13:05   ` Jinjie Ruan
2026-09-11 12:56     ` Will Deacon
2026-09-16  2:34       ` Jinjie Ruan
2026-09-07 16:40 ` [PATCH 19/19] arm64: smp: Harden parallel CPU bringup against broken PSCI firmware Will Deacon
2026-09-08 13:36   ` Will Deacon

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