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charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=D5VK6/Rj c=1 sm=1 tr=0 ts=692e96e0 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=yv61VyXJEuW5_bWReSAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2IAK7mSb01TDkoV9MhbyA1W5jNtyE3u2 X-Proofpoint-GUID: 2IAK7mSb01TDkoV9MhbyA1W5jNtyE3u2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAyMDA1OSBTYWx0ZWRfX/vpbMyslI4p8 8E4vAY6on/WYnN6cpNLwRsYklKt1m8wXuD0w/NFAIv80E9g4cnJ9fzDgkhKpZau2IoX6Ye+pIcj DCjyruI9UYr1D5ADHga6NmprfZcG2gamAz46NIO7KMCbhK1S82xz1EznUYzTtPoXmr1EF59Wltj ZME+wKNu05Jt72XCfa0bugsq/j502odGRDQwCom3Pg/S+AXb4YDipr9cMn5QlbLGQWs6LhOx4hS OmELr85DbSJmPGKfu8rLtCIFLLnBnpbOffShRrBZ8fjdfvvxNbdDc100VDBejrmhjJhu5r5wWi/ Ng/Wyy9iKDDYbVWvUHx5K/1i8JMXMlSXQkycnbdw3z5erAnlM6/MhTyaT60CWG0fDkxXyObzDqT K4PB3yIQGkt6wIbY20raeNVfoOpymQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512020059 On 11/26/25 9:10 AM, Vikram Sharma wrote: >> From: Nihal Kumar Gupta >> >> Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). >> Compared to Lemans, the key difference is in SDA/SCL GPIO assignments >> and number of CCIs. > [...] > >> @@ -5071,6 +5182,240 @@ tlmm: pinctrl@f100000 { >> #interrupt-cells = <2>; >> wakeup-parent = <&pdc>; >> >> + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { >> + pins = "gpio73"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-disable; >> + }; > I'm not sure whether I was unclear, but my intention was to ask you to move the MCLK pin definitions to the SoC DTSI, because that comes from the design of the platform and doesn't vary between end products. > > GPIO_73 being related to a voltage regulator is strictly a property of the EVK. MCLK pin definitions are already present under the tlmm block in SoC dtsi(monaco.dtsi) as required by the pinctrl subsystem(qcom,qcs8300-tlmm.yaml). Are you suggesting they shouldn’t be part of TLMM in the SoC DTSI? This doesn’t align with the YAML file. Regarding GPIO_73: Noted. I will move it to monaco-evk.dts under the tlmm section. Below are the example snippets: In monaco.dtsi (SoC level): tlmm: pinctrl@... { cam_mclk0_default: cam-mclk0-default-state { pins = "gpio67"; function = "cam_mclk"; drive-strength = <2>; }; .... }; In monaco-evk.dts (Board level): &tlmm { cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { pins = "gpio73"; function = "gpio"; drive-strength = <2>; bias-disable; }; ... }; -- Regards, Nihal Kumar Gupta