From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751653AbdCJGNJ (ORCPT ); Fri, 10 Mar 2017 01:13:09 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:38844 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750806AbdCJGNI (ORCPT ); Fri, 10 Mar 2017 01:13:08 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8FC7860808 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org Subject: Re: [PATCH v5 3/4] dt-bindings: phy: Add support for QMP phy To: Bjorn Andersson References: <1489050441-3240-1-git-send-email-vivek.gautam@codeaurora.org> <1489050441-3240-4-git-send-email-vivek.gautam@codeaurora.org> <20170309110733.GB53510@Bjorns-MacBook-Pro-2.local> Cc: robh+dt@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, sboyd@codeaurora.org, srinivas.kandagatla@linaro.org, Rob Herring From: Vivek Gautam Message-ID: <3f6596d9-d1e3-324c-10fb-6c3e65ba724b@codeaurora.org> Date: Fri, 10 Mar 2017 11:43:00 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20170309110733.GB53510@Bjorns-MacBook-Pro-2.local> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/09/2017 04:37 PM, Bjorn Andersson wrote: > On Thu 09 Mar 10:07 CET 2017, Vivek Gautam wrote: > > [..] >> + phy@34000 { >> + compatible = "qcom,msm8996-qmp-pcie-phy"; >> + reg = <0x034000 0x488>; > Drop the leading 0 from the address. Okay, will drop it. > >> + #clock-cells = <1>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, >> + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_CLKREF_CLK>; >> + clock-names = "aux", "cfg_ahb", "ref"; >> + >> + vdda-phy-supply = <&pm8994_l28>; >> + vdda-pll-supply = <&pm8994_l12>; >> + >> + resets = <&gcc GCC_PCIE_PHY_BCR>, >> + <&gcc GCC_PCIE_PHY_COM_BCR>, >> + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; >> + reset-names = "phy", "common", "cfg"; >> + >> + pciephy_0: lane@0 { > The "@xyz" part should match the first value in "reg", i.e. 35000 here. Right, i think this came from my older version of patches. Will correct it. Regards Vivek > >> + reg = <0x035000 0x130>, >> + <0x035200 0x200>, >> + <0x035400 0x1dc>; >> + #phy-cells = <0>; >> + >> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; >> + clock-names = "pipe0"; >> + resets = <&gcc GCC_PCIE_0_PHY_BCR>; >> + reset-names = "lane0"; >> + }; >> + >> + pciephy_1: lane@1 { >> + ... >> + ... >> + }; > Regards, > Bjorn -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project