Re: x86/amd late microcode thread loading slows down boot

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 14/11/2024 9:56 am, Borislav Petkov wrote:
> On Thu, Nov 07, 2024 at 09:58:12PM +0100, Thomas De Schampheleire wrote:
>> Boris, perhaps you can propose a more fine-tuned flushing? I'd be happy to try
>> that.
> Let's see if that does the deal too.
>
> Thx.
>
> ---
> diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h
> index 580636cdc257..4d3c9d00d6b6 100644
> --- a/arch/x86/include/asm/tlb.h
> +++ b/arch/x86/include/asm/tlb.h
> @@ -34,4 +34,8 @@ static inline void __tlb_remove_table(void *table)
>  	free_page_and_swap_cache(table);
>  }
>  
> +static inline void invlpg(unsigned long addr)
> +{
> +	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");

"invlpg %0" :: "m" (*(char *)addr) : "memory"

The compiler can usually do a better job than forcing it into a plain
register.

> +}
>  #endif /* _ASM_X86_TLB_H */
> diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
> index 31a73715d755..6a73f775ce4c 100644
> --- a/arch/x86/kernel/cpu/microcode/amd.c
> +++ b/arch/x86/kernel/cpu/microcode/amd.c
> @@ -34,6 +34,7 @@
>  #include <asm/setup.h>
>  #include <asm/cpu.h>
>  #include <asm/msr.h>
> +#include <asm/tlb.h>
>  
>  #include "internal.h"
>  
> @@ -489,6 +490,9 @@ static int __apply_microcode_amd(struct microcode_amd *mc)
>  
>  	native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code);
>  
> +	if (x86_family(bsp_cpuid_1_eax) == 0x17)
> +		invlpg((u64)(long)&mc->hdr.data_code);

Ok, so it's Fam17h specific.  That's good to know.  Any formal statement
on the matter from AMD ?

However, these blobs are 3200 bytes long and come with a good chance of
crossing a page boundary.   If you're invlpg'ing, you need to issue a
second one for the final byte of the image too.

~Andrew