From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C812D9499 for ; Thu, 19 Mar 2026 14:54:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773932051; cv=none; b=ss8PAI7nvsJkMo4B36MzTW8X+bB6aHukdn2WOB4WOEnXc9gBhLDwzNXtEm8A/J2bl7KU43DYpiSfLU8wM8gWCnxeZbNi9HL8//iSiqwJeAwndfcF/0hIVMcn6wnBReO93XyY4FuLoKGio9O6heB/y6+9eJxUavK5ehDRset3dAM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773932051; c=relaxed/simple; bh=ogaWxCjijDVcPcWs+oqcUcgpVtLeEpTz+9Padk7Av/U=; h=Message-ID:Date:MIME-Version:From:Subject:To:Cc:References: In-Reply-To:Content-Type; b=RSOTm8RRQeeWfQWJtl0om9QJtmrDmpG+YHUN68Rxn6Y5e67smTrK5nU/h3IOW5EZrM1w+jPKfcjG0Jz4yEl6imzdEYMkBKAMbl/F5VGo6iyrOokp6g3jRkhyB3goQ68ZhQfik9H8zpmpnKI4lDVZsnTA8Ijh2buxuWkIXbgPvSs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=XDKawPQv; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XDKawPQv" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso8620895e9.1 for ; Thu, 19 Mar 2026 07:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1773932048; x=1774536848; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:organization:autocrypt :content-language:references:cc:to:subject:reply-to:from:user-agent :mime-version:date:message-id:from:to:cc:subject:date:message-id :reply-to; bh=fYfxz+rNELIteGsbKAMavpc3Lvzth4lh50wrsIwCT58=; b=XDKawPQvBL7Mjc9CoTWGI8wActlJm6DmT3ai+tDO92lsfnzpviNoyHvEzqyihuCRoq C4ZZu2Cz5/6w2GNsyrjBJBlklmbhykks0zV2EwUHFK24V3YBqYor4hyCIncVGb2GLmyg dx5Y26egCaPdq4G8KMYesdRU2szFRHELtsg8T25hyk56+Xc5f2moFjx+QyetaglUFl9a Mqawg3TtRNSlNfrUznAMAoxZTGw9GU5q59CKf9NZwDkFj2bOPb+SAQQ/Cs4sfCzDCSm+ KhlJvIc9DY5/nW6iPfsTqFP9d/34An7l7/FSjoiVSIIgGSlpIZypeQdnJIm5XzD7D4wq Adzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773932048; x=1774536848; h=content-transfer-encoding:in-reply-to:organization:autocrypt :content-language:references:cc:to:subject:reply-to:from:user-agent :mime-version:date:message-id:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fYfxz+rNELIteGsbKAMavpc3Lvzth4lh50wrsIwCT58=; b=PTHq2R5FBua645nBhJlkuNd3yExRXGMkT9gyQISid+WHEgPJmpAfx8KylRSDO0QtTh ZAJ8rvdQ0ispp9LsA7wdE3imx6QtdGa2tqoR3Aqp9GBSpiWFI8izMqqVBex8g8VGolBC sgRgqF0bELxMqyfhJTT5sU5U9/C7aGFUpeh4dnftMcGPVUm+u0L506gcHnH9MfgHu4EH 6GscvcXlSNmTF4kUdT1rJvFGxmJYA7sJrpNtE9lUciiKEgVkNiNmdNnxTz2i2ajpPnkX Vzov/S92v2+G95oDw9VZZy+bF7KK7jiTCSbm0k4UYZirU3Yy2L3URzDtGlq6yu7xl80f cySA== X-Forwarded-Encrypted: i=1; AJvYcCW117hBetASmz9RvFjG0qrawTs0VJKiJjICPVRpaI90zxaKMLB71jHOJ1h4/FP0Lt66awxxpTmx7IdBRYM=@vger.kernel.org X-Gm-Message-State: AOJu0Yxg9vavtdlbgoZW+aWRP58sbox5IvRoHwj7oFPGz0yVhE/ye4u9 p/YljvPSdfiYaWYkbwH53KB34l/Hz9icipTMtA/Xt0PCva/CS9HvQL7hJ7DP19Ei4oE= X-Gm-Gg: ATEYQzxhYn/VA1p/1ncOS8okOlk3cfe+C8cBK2DtVboQzH/pDIkasJv8UlSZkHTDOVs Fo2siXVGPgznEoHwL4EZbeSrxt4Nnk5Pc3deD2ONWXS4vKP33bUKOzUiw43FA05AtpYVmez7jza zqbl/f+4Du9yJPHwElOs1sEKJJVbqoF8/cj57oRYCYw6ie8ZgzqF/N000wdklOfjp39oeoXteY+ XCskdeMZP+cGIpYidDUXqmd0a0bhUYwWQypOHnHJGnX2ozdZgOkGgioekr1aRz1HDAt6Ys2C0o+ qB0WNSm8CRqpCzLECylTvCwyS4J0XYncghjuVMHKI13lfeBwFiHF0WfEFOUH2tfHjo3o99meGxb LV03r46WRidxQb+McPbQrGwZjj3yB0sXXzRMeIJY8CH548duOpL4W/7EhoXT9pIw3PqvEb+mN/R i4RS7uWagSEUs4UImOrTMN+aWkDi3o4oVElna9JMDETz0DclkABS4JcuVx3A7GkgqCyvnZ45Fg1 WamfCc= X-Received: by 2002:a05:600c:8b2e:b0:485:2a4b:7bc3 with SMTP id 5b1f17b1804b1-486f4440fb2mr118026975e9.4.1773932047740; Thu, 19 Mar 2026 07:54:07 -0700 (PDT) Received: from ?IPV6:2a01:e0a:106d:1080:8e54:fbaf:8cb6:e9f7? ([2a01:e0a:106d:1080:8e54:fbaf:8cb6:e9f7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b5184962bsm16678526f8f.7.2026.03.19.07.54.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Mar 2026 07:54:07 -0700 (PDT) Message-ID: <3f8763af-aad2-4d92-90c8-cfd290212503@linaro.org> Date: Thu, 19 Mar 2026 15:54:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation To: Alexander Koskovich Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> <3gLK4s97giqqXagfHKhfiIHbfbl2snwfOj9dcTNGPUYi10w9-1EdATqzz1LPCVTpz4bLFYOm8u_Fl8PfC7t5yabows4UCzRKVwjraEWW6hc=@pm.me> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <3gLK4s97giqqXagfHKhfiIHbfbl2snwfOj9dcTNGPUYi10w9-1EdATqzz1LPCVTpz4bLFYOm8u_Fl8PfC7t5yabows4UCzRKVwjraEWW6hc=@pm.me> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/19/26 15:40, Alexander Koskovich wrote: > On Thursday, March 19th, 2026 at 10:13 AM, Neil Armstrong wrote: > >> Hi, >> >> On 3/19/26 12:58, Alexander Koskovich wrote: >>> Using bits_per_component * 3 as the divisor for the compressed INTF >>> timing width produces constant FIFO errors for the BOE BF068MWM-TD0 >>> panel due to bits_per_component being 10 which results in a divisor >>> of 30 instead of 24. >>> >>> Regardless of the compression ratio and pixel depth, 24 bits of >>> compressed data are transferred per pclk, so the divisor should >>> always be 24. >> >> Not true with widebus, specify why 24 and because DSI widebus is not implemented yet. >> >>> >>> Signed-off-by: Alexander Koskovich >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++----- >>> 1 file changed, 4 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> index 0ba777bda253..5419ef0be137 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( >>> } >>> >>> /* >>> - * for DSI, if compression is enabled, then divide the horizonal active >>> - * timing parameters by compression ratio. bits of 3 components(R/G/B) >>> - * is compressed into bits of 1 pixel. >>> + * For DSI, if DSC is enabled, 24 bits of compressed data are >>> + * transferred per pclk regardless of the source pixel depth. >>> */ >>> if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { >>> struct drm_dsc_config *dsc = >>> dpu_encoder_get_dsc_config(phys_enc->parent); >>> + >> Drop this change >> >>> /* >>> * TODO: replace drm_dsc_get_bpp_int with logic to handle >>> * fractional part if there is fraction >>> */ >>> - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / >>> - (dsc->bits_per_component * 3); >>> + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24; >> >> It would be helpful to somehow show that 24 is 8 * 3, 8 being the byte width and 3 the compression ratio. > > Can you clarify what the 3 represents? My panel should have a 3.75:1 compression > ratio (30/8) so the final divisor of 24 would be wrong for my panel if its the > compression ratio? So my guess is that while the exact ratio on the DSI lanes is 3.75:1, the ratio used to calculate the INTF timings is 3, then the DSC encoder probably does the magic to feed 10bpp into a 3.75:1 ratio over the DSI lanes. In dsi_adjust_pclk_for_compression, the pclk is adjusted to take in account bits_per_component, so I presume the actual DSI pclk _is_ timing->width * drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3), which is your 3.75:1, but the INTF needs to generate timing->width * drm_dsc_get_bpp_int(dsc) / (8 * 3) pixels to the DSC encoder which will emit timing->width * drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3) pixels. In any case, 24 _is_ 3 * 8, 3 being the DSC compression ratio on the INTF side. Dmitry, Konrad, could you help confirming this ? Neil > >> >>> timing->xres = timing->width; >>> } >>> } >>> >> >> >> > > Thanks, > Alex