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Mon, 26 Oct 2026 15:49:10 -0700 (PDT) Received: from [192.168.1.12] ([31.94.68.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a04ad39sm587066755e9.1.2026.10.26.15.49.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 15:49:09 -0700 (PDT) Message-ID: <3ff4ef96-9c59-4e8d-a0da-92a1ac6f5ba1@gmail.com> Date: Mon, 26 Oct 2026 22:49:08 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: amd-gfx@lists.freedesktop.org Cc: Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , Harry Wentland , Leo Li , Rodrigo Siqueira , Mario Limonciello , David Airlie , Simona Vetter , Richard Lane , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org From: Richard Lane Subject: [PATCH 3/3] drm/amd/display: report synced Apple 5K tiles to PowerPlay for MCLK switch Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit When driving both 2560x2880 tiles of an Apple 5K iMac panel, Display Core's program_timing_sync() already aligns both CRTCs in hardware during dc_commit_streams() because the two streams share identical timings. However, on DCE < 12 (iMac15,1 through Polaris-based iMac19,1), Display Core leaves pp_display_cfg.all_displays_in_sync unset. Because PowerPlay is not informed that the two streams have synchronized vertical blanking intervals, SMU7 prevents MCLK switching at idle or causes modeset underflows. Report all_displays_in_sync = true to PowerPlay after committing both tiled streams so SMU7 knows the tiles blank simultaneously and can safely downclock MCLK at idle. Signed-off-by: Richard Lane --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 548f975c7324..384a81371f80 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4788,6 +4788,19 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, mutex_lock(&dm->dc_lock); dc_exit_ips_for_hw_access(dm->dc); WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); + /* + * DCE < 12 leaves all_displays_in_sync unset; report synchronized + * Apple 5K tiles to PowerPlay after commit so SMU7 can downclock MCLK + * at idle without modeset underflows. + */ + if (params.stream_count == 2 && + params.streams[0]->link->tiled_peer == params.streams[1]->link) { + struct dm_pp_display_configuration *pp_cfg = + &dm->dc->current_state->pp_display_cfg; + + pp_cfg->all_displays_in_sync = true; + dm_pp_apply_display_requirements(dm->dc->ctx, pp_cfg); + } bool frl_stream_found = false; -- 2.55.0