From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C980423BCF5 for ; Wed, 2 Apr 2025 13:59:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743602398; cv=none; b=cGcNK2IcZUojGfxLzqLP1AtYT3+YcgJD7Q4xndGEg0OVVRLDX58OgaX/l6KoUp0FVtOYfNCU6cM+1lnObajsXWX0zqkC2xtEleBsNSF7Pc/nH7m3d1eRfDx4Tv8UICXfosHuNZUiIav1r1iQRWOZjc2LVcFqhbIDp4MvP6kfEgA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743602398; c=relaxed/simple; bh=/4DaEGIXW044d5Cp6y0Go9pn44Yqu5BwIGbuF/5NnPg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=CS0wsmUoT6r4XLhNIU3ThL4IX0MQV6pkQP8Rbv2TEqCOrv+IX8Lc77kTXDhUp0za5IIji+pPZegn+easWTDLC1HS44PNqvQJM+GKAeZl2jLS2CuapyJAxRChCOLzaEyec3A5G1n/NyOLlB7tnLjLM+e8RCU0QW4YQj0Ru6MAXpk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=o/sYsEgs; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="o/sYsEgs" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 687186A2; Wed, 2 Apr 2025 15:58:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1743602282; bh=/4DaEGIXW044d5Cp6y0Go9pn44Yqu5BwIGbuF/5NnPg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=o/sYsEgsM8snr1va7GPLJuvk+/RkfQw87WQmvP4kFt4xa7umWK8F2cmxKkQEnaX6r k2duMI/kT0ycPpZuIbK2xj1RbsiELaBgJJSenp1loV0YzR5BvmOBo+mwLijcmAm459 0UKCViWg906d0Y2ZsprUwATb955oZzCdoShVC/1Q= Message-ID: <4015caef-1afb-4c3f-8768-a3a5d51390a0@ideasonboard.com> Date: Wed, 2 Apr 2025 16:59:51 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine To: Devarsh Thakkar Cc: sakari.ailus@linux.intel.com, u.kleine-koenig@baylibre.com, vigneshr@ti.com, aradhya.bhatia@linux.dev, s-jain1@ti.com, r-donadkar@ti.com, vkoul@kernel.org, kishon@kernel.org, mripard@kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250326152320.3835249-1-devarsht@ti.com> <20250326152320.3835249-3-devarsht@ti.com> <5465d2dd-d81a-4e33-b76f-cbbd3386c725@ideasonboard.com> <223da324-4de7-4e62-b001-ea89c4768a13@ti.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 02/04/2025 16:35, Devarsh Thakkar wrote: > Hi Tomi, > > Thanks for the review. > > On 02/04/25 17:12, Tomi Valkeinen wrote: >> Hi, >> >> On 26/03/2025 17:23, Devarsh Thakkar wrote: >>> Use system characterized reset value specified in TRM [1] to program >>> calibration wait time which defines number of cycles to wait for after >>> startup state machine is in bandgap enable state. >>> >>> This fixes PLL lock timeout error faced while using RPi DSI Panel on >>> TI's >>> AM62L and J721E SoC [2]. >>> >>> [1] AM62P TRM (Section ): >>> https://www.ti.com/lit/pdf/spruj83 >>> >>> [2]: >>> Link: https://gist.github.com/devarsht/89e4830e886774fcd50aa6e29cce3a79 >>> >>> Cc: stable@vger.kernel.org >>> Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") >>> Signed-off-by: Devarsh Thakkar >>> --- >>> V2: Introduced this as as separate patch >>> >>>   drivers/phy/cadence/cdns-dphy.c | 3 +++ >>>   1 file changed, 3 insertions(+) >>> >>> diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/ >>> cdns-dphy.c >>> index c4de9e4d3e93..11fbffe5aafd 100644 >>> --- a/drivers/phy/cadence/cdns-dphy.c >>> +++ b/drivers/phy/cadence/cdns-dphy.c >>> @@ -30,6 +30,7 @@ >>>   #define DPHY_CMN_SSM            DPHY_PMA_CMN(0x20) >>>   #define DPHY_CMN_SSM_EN            BIT(0) >>> +#define DPHY_CMN_SSM_CAL_WAIT_TIME    GENMASK(8, 1) >>>   #define DPHY_CMN_TX_MODE_EN        BIT(9) >>>   #define DPHY_CMN_PWM            DPHY_PMA_CMN(0x40) >>> @@ -405,6 +406,8 @@ static int cdns_dphy_configure(struct phy *phy, >>> union phy_configure_opts *opts) >>>       reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | >>>             FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); >>>       writel(reg, dphy->regs + DPHY_BAND_CFG); >>> +    writel(FIELD_PREP(DPHY_CMN_SSM_CAL_WAIT_TIME, 0x14) | >>> DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, >>> +           dphy->regs + DPHY_CMN_SSM); >> >> This sounds like a TI specific characterized value, but the function >> here is a generic one. Also, is the value same for all TI SoCs? Or is >> it per-soc? >> > > No this is not TI specific value. As mentioned in commit message, 0x14 > is the cadence characterized default value for calibration wait time > which they put in as reset value in the IP (if you reset the IP you will > see calibration wait time as 0x14) to be used by software for optimal > initialization. If it's a register default value, why do you need to write it? Also, why do you say "characterized reset value"? I can't find any reference to this in the TRM (in the patch you point to the TRM, but not where to find the data there). The reset value of 0x14 could be just a default value, not characterized at all. And if this is a bandgad related wait timeout, shouldn't it be set before the BAND_CFG registers? Although It's not clear what those do. Tomi