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Mon, 27 Nov 2023 10:43:44 -0600 Message-ID: <401bc91f-f558-8185-8f14-dd1ef41aef17@amd.com> Date: Mon, 27 Nov 2023 08:43:44 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 5/5] dmaengine: xilinx: xdma: Ease dma_pool alignment requirements Content-Language: en-US To: Jan Kuliga , , , , , , , References: <20231124192524.134989-1-jankul@alatek.krakow.pl> <20231124192558.135004-6-jankul@alatek.krakow.pl> From: Lizhi Hou In-Reply-To: <20231124192558.135004-6-jankul@alatek.krakow.pl> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|SJ2PR12MB9191:EE_ X-MS-Office365-Filtering-Correlation-Id: 0de92afe-1fa6-4583-a588-08dbef680618 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PVhWfiJTRzEiikLj+CILRLb6SOJRLuB1TztsksV1SF4V1IPzTVFOclKG6MXSvWfG7zh4QhNZqiVkIMx80Ph3VUaLewrmJ6d6TvwIeC8Wefgn7p6dhMeTpOAD0EOh02MFXLN/hfIZAMEkFP1Gnlv102rRIe0DoM8JQJ6JUDoSb+Ki26N58VBqD7g5N7VmLkW/PgtXrmOROtOYjT94u0HOI+Brciwbpqamfe82Lyh8m1LTunZOSrQRbUYqFC1STnaPgHn+WbdFakQibNGnUhmFFSSX18awJAsFKzIp/wGQ6X33jX+q/8/bZIpScEnpEKmav/AiwLjtjm6OyJA7KbXD6ekn542Mz8THNojImemiCMygJ7rIEovy+plOEKuQ1jlbzBzyrepWBS2a22XwM598VuvewqoIo/vEj78oCJllq5nLtR16IDPj8bGVW1Tv/59tkfRwHT0Wc8B9ug3hMZsc4gfgXlYgGE9Z1df9yiEam2+SKqWZ92BM8a4bVJDi2SaQgVPrR4VFcty1lvhB6OAh6b32OuIkKdbrLDqKd1akjjLrjcQFSY/o0yeeEDObAFWGaDMyGnqxKj+6gDdcsKrKJw5HmIKHsZSIQm0z+WCtl5Br1UIgs2Bxhpqcs1LYTsmwYdWUPITsfm2m09nwtAzTgocksoZHX7jXsoTKn6OpB8vJBXZmv3FI3xYYNgajWrRXY3NMQo89NpXFBo2d0FkR9ZlMnlPSPRmXHwWEJXbkANhqjnlTNJFlnnhj4S+emiol+dFHRBCeypMDW8ij8G/+usFk0/26Msf3cJLbVy3hjqJcOGwPWTYvrMLFlJxeZCKf X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(230922051799003)(1800799012)(82310400011)(64100799003)(186009)(451199024)(36840700001)(40470700004)(46966006)(40480700001)(41300700001)(36756003)(31686004)(81166007)(47076005)(356005)(36860700001)(336012)(83380400001)(426003)(5660300002)(82740400003)(70206006)(26005)(44832011)(86362001)(2616005)(2906002)(70586007)(53546011)(8676002)(8936002)(31696002)(478600001)(40460700003)(16576012)(6636002)(110136005)(316002)(43740500002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2023 16:43:45.9410 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0de92afe-1fa6-4583-a588-08dbef680618 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9191 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/24/23 11:25, Jan Kuliga wrote: > According to the XDMA datasheet (PG195), the address of any descriptor > must be 32 byte aligned. The datasheet also states that a contiguous > block of descriptors must not cross a 4k address boundary. Therefore, > it is possible to ease the pressure put on the dma_pool allocator > just by requiring sufficient alignment and boundary values. Add proper > macro definition and change the values passed into the > dma_pool_create(). > > Signed-off-by: Jan Kuliga > --- > drivers/dma/xilinx/xdma-regs.h | 7 ++++--- > drivers/dma/xilinx/xdma.c | 6 +++--- > 2 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h > index 6bf7ae84e452..d5cb12e6b8d4 100644 > --- a/drivers/dma/xilinx/xdma-regs.h > +++ b/drivers/dma/xilinx/xdma-regs.h > @@ -64,9 +64,10 @@ struct xdma_hw_desc { > __le64 next_desc; > }; > > -#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc) > -#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) > -#define XDMA_DESC_BLOCK_ALIGN 4096 > +#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc) > +#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) > +#define XDMA_DESC_BLOCK_ALIGN 32 > +#define XDMA_DESC_BLOCK_BOUNDARY 4096 > > /* > * Channel registers > diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c > index de4615bd4ee5..d32ae93e18b6 100644 > --- a/drivers/dma/xilinx/xdma.c > +++ b/drivers/dma/xilinx/xdma.c > @@ -735,9 +735,9 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan) > return -EINVAL; > } > > - xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), > - dev, XDMA_DESC_BLOCK_SIZE, > - XDMA_DESC_BLOCK_ALIGN, 0); > + xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev, > + XDMA_DESC_BLOCK_SIZE, XDMA_DESC_BLOCK_ALIGN, > + XDMA_DESC_BLOCK_BOUNDARY); > if (!xdma_chan->desc_pool) { > xdma_err(xdev, "unable to allocate descriptor pool"); > return -ENOMEM; This is probably not needed. The 32 adjacent descriptors here is 1024 bytes. Defining 4k alignment should be good enough. Thanks, Lizhi