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Wed, 15 Jul 2026 03:45:52 -0700 (PDT) X-Received: by 2002:a05:620a:4721:b0:92e:601b:8d43 with SMTP id af79cd13be357-92ef2af9c3emr1426627985a.1.1784112352422; Wed, 15 Jul 2026 03:45:52 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c168716f6dbsm3186566b.15.2026.07.15.03.45.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Jul 2026 03:45:51 -0700 (PDT) Message-ID: <401ee2b2-1d82-40b0-95aa-005840a5078f@oss.qualcomm.com> Date: Wed, 15 Jul 2026 12:45:48 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] irqchip/irq-qcom-mpm: Register MPM under CPU cluster power domain To: Stephan Gerhold Cc: Sneh Mankad , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Shawn Guo , Marc Zyngier , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260713-b4-shikra_lpm_addition-v1-0-3d858df2cbbf@oss.qualcomm.com> <20260713-b4-shikra_lpm_addition-v1-2-3d858df2cbbf@oss.qualcomm.com> <7c8178ec-8bab-4427-8faa-5b28cb76a5ad@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDEwNCBTYWx0ZWRfX79jeCL7H4OEU QsTVoQZtjQEx09Sb1DEVmJGcQj2Lzba6gSLRej+W+yzmKbKdoKUw7hccTJpcInQMJ2KI5ht6XID tam0iCtqHDHm51dfgNUbaBnfT2lYGe/dLvmEXwRVgi/CcfKKOH6kGmSLO6EkbdvITRoQxCUcoHy o4r9nBSSy9//NNwEwsLhqEDRJ/bN/+k4kieepmV9aohERIBPQolRvB4QPgUvBALuea3un0UGz7k iELUyBeUcrAevsFW6StKyAif8CldpEV+rzEHzPoBf8Vb0sL73UPS+WV2/9QBfvgBc4YwYe2ovT+ vMWkVx0a/0DXNX+lscxWAlOj9342Jv2XRSwmwnDAJuGgwpVR3ho/TXWDhvOpnvVxadwVnJq2eE8 afwalgcHffmGnSmXzA0ZYLSh5dA69Oz5ysD4wCVHgv5HcCOx++zbHv9l3VkSAI6TOVZg0rF01v8 AkABq6VYm6Ph299gBNQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDEwNCBTYWx0ZWRfX/6aVHQNOSnlc LFS6SBnmfdEaEnJqQ67ngIyAES3ze9A7j7iaHI/93L++tVl9QsqKpCKJF4RyaTuatyJv7EpL1at uOVA7QKVdMeBWUGrODtnAHft61v013g= X-Authority-Analysis: v=2.4 cv=bKcm5v+Z c=1 sm=1 tr=0 ts=6a5764e2 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=ERnfXskPEjP3n-q0xIsA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: BgrdJpSs_D21u94WPpqV_YjBWBsdBXGs X-Proofpoint-GUID: BgrdJpSs_D21u94WPpqV_YjBWBsdBXGs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150104 On 7/15/26 12:34 PM, Stephan Gerhold wrote: > On Wed, Jul 15, 2026 at 11:46:58AM +0200, Konrad Dybcio wrote: >> On 7/13/26 12:25 PM, Sneh Mankad wrote: >>> MPM irqchip needs to notify RPM (Resource Power Manager) processor to read >>> the latest wake up capable interrupts when the CPU cluster is entering the >>> deepest idle state. This is done by sending IPC interrupt to RPM and is >>> implemented as .power_off() callback by registering MPM as parent power >>> domain to CPU cluster. >> >> [...] >> >>> If MPM has not registered with CPU cluster power domain, utilize the CPU PM >>> notifications to manage RPM communication when the last CPU goes to power >>> collapse. >> >> I have mixed feelings about this case. The RPMH RSC driver keeps that as a >> fallback for platforms which don't have PSCI OSI mode specifically. >> >> On the other hand, there are platforms (early arm64 - pre-msm8996 and almost >> all of the arm32 platforms) that don't define any CPU power domains, so >> perhaps it's necessary after all.. >> > > I don't think this fallback is relevant for the non-PSCI QC platforms, > for the following reasons: > > - They don't define the MPM. > - They don't support cluster idle upstream, so they don't need to > define the MPM. They can't reach the idle state where it would become > relevant. > - The setup for cluster idle without PSCI is essentially equivalent to > OSI, except that the SPM/SAW driver needs to program the idle state > to enter. There is one SPM/SAW for every idle domain (e.g. on > MSM8939: 2x4 CPU, 2x Cluster, 1x System). You can just model the > SPM/SAW instances as power domains to get the same setup as PSCI OSI > (I had a draft for this at some point). So if someone ever implements > this, we should be able to use the same approach as for PSCI OSI. Yeah I said 'necessary' because of the arm32 platforms. This would probably be the preferable way forward. > I'm not aware of non-OSI PSCI platforms with MPM either, so I'm not sure > when this fallback would be used. I think it's generally only SC7180 and there's definitely no MPM there. > We probably do need some fallback for the old sm6375/agatii DTBs though. The sleep logic doesn't really matter without the platforms hitting a specific power state anyway, so I'm not sure we actually have to (i.e. the regressed path can't be exercised today anyway) Konrad