From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760667AbcJRNE4 (ORCPT ); Tue, 18 Oct 2016 09:04:56 -0400 Received: from relay3.sgi.com ([192.48.152.1]:45546 "EHLO relay.sgi.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1760546AbcJRNEh (ORCPT ); Tue, 18 Oct 2016 09:04:37 -0400 Subject: Re: [PATCH] ALSA: hda - allow 40 bit DMA mask for NVidia devices To: Ard Biesheuvel References: <1476721439-29519-1-git-send-email-ard.biesheuvel@linaro.org> CC: Takashi Iwai , , , "linux-kernel@vger.kernel.org" From: Mike Travis Message-ID: <40321a07-bff4-4293-d85b-bddba31d1c33@sgi.com> Date: Tue, 18 Oct 2016 06:04:31 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [134.15.31.45] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/18/2016 5:49 AM, Ard Biesheuvel wrote: > On 18 October 2016 at 13:46, Mike Travis wrote: >> >> Have you tested this change on a system which has physical >> addressing > 40 bits to insure that addresses > 40 bits are >> not simply truncated to an incorrect (mod 40) address? > > The device should never see addresses > 40 bits, given that the DMA > mask is set to 40 bits not 64. I agree that the device should never see that. But how is that restriction imposed? If a user presents an buffer address > 40 bits how would that be converted to useful buffer at <= 40 bits? I believe I tried this (at the time the kernel was at version 2.6) and it did not work. Since audio I/O was such a low (relative) bandwidth, it was not worth the effort to rework the audio code to allow buffers > 32 bits but <= 40 bits. It may have changed since then? > >> By not restricting the addresses to 32 bits you are not >> restricting the device to the DMA32 zone. >> >> This is what caused the original panic on UV systems. >> >> Btw, the newest nVidia GPUs have > 40 bits of DMA address bits. >> > > Thanks, > Ard. >