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([2600:8803:e7e4:500:f242:ecd6:f61e:d764]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7e9aa57a229sm4889712a34.4.2026.06.27.13.05.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 27 Jun 2026 13:05:35 -0700 (PDT) Message-ID: <40485b4e-6585-42a1-9b84-3019328574c5@baylibre.com> Date: Sat, 27 Jun 2026 15:05:34 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: iio: adc: Add Nuvoton MA35D1 EADC To: Chi-Wen Weng , jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: nuno.sa@analog.com, andy@kernel.org, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20260625110638.38438-1-cwweng.linux@gmail.com> <20260625110638.38438-2-cwweng.linux@gmail.com> Content-Language: en-US From: David Lechner In-Reply-To: <20260625110638.38438-2-cwweng.linux@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/25/26 6:06 AM, Chi-Wen Weng wrote: > From: Chi-Wen Weng > > Add devicetree binding for the Enhanced ADC controller found on > Nuvoton MA35D1 SoCs. > > The controller has one register region, one interrupt and one functional > clock. ADC inputs are described using standard channel child nodes, > including optional differential channel pairs. > > Signed-off-by: Chi-Wen Weng > --- > .../bindings/iio/adc/nuvoton,ma35d1-eadc.yaml | 100 ++++++++++++++++++ > 1 file changed, 100 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml > > diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml b/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml > new file mode 100644 > index 000000000000..ae7ad0f7689a > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,ma35d1-eadc.yaml > @@ -0,0 +1,100 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/nuvoton,ma35d1-eadc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton MA35D1 Enhanced Analog to Digital Converter > + > +maintainers: > + - Chi-Wen Weng > + > +description: | > + The Nuvoton MA35D1 Enhanced Analog to Digital Converter (EADC) is a > + 12-bit ADC controller integrated in the MA35D1 SoC. Each enabled ADC > + input is described by a child channel node. > + > +properties: > + compatible: > + const: nuvoton,ma35d1-eadc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 Datasheet says there are 4 interrupts. > + > + clocks: > + maxItems: 1 Should there be an optional vref-supply for the V_REF pin? Should there be a dmas property? Datasheet says it supports PDMA transfer. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^channel@[0-8]$': > + type: object > + $ref: adc.yaml > + unevaluatedProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 8 I assume 8 is for the internal batter voltage channel? Often, we don't include fixed internal channels like this in the devicetree since they are always the same and don't depend on external wiring. > + > + diff-channels: > + minItems: 2 > + maxItems: 2 adc.yaml already specifies minItems and maxItems, so we don't need to repeat it. > + items: > + minimum: 0 > + maximum: 8 This (and reg) are uint32, so don't really need minimum: 0. Also, I assume that 8 is for the internal battery voltage channel, which wouldn't make sense as part of a differential input. > + > + required: > + - reg > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + adc@40430000 { > + compatible = "nuvoton,ma35d1-eadc"; > + reg = <0x0 0x40430000 0x0 0x10000>; > + interrupts = ; > + clocks = <&clk EADC_GATE>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + channel@0 { > + reg = <0>; > + }; > + > + channel@1 { > + reg = <1>; > + }; > + > + channel@2 { > + reg = <2>; > + diff-channels = <2 3>; > + }; > + }; > + }; > +...