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Thu, 02 Oct 2025 02:35:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGUdKY/s60So/cK9CP2fZSoDUz/GJTA6OYSgtEOsSuT0tjAiYtF/JKWQr4BbsZy/WrKkHirUQ== X-Received: by 2002:a17:90b:4a87:b0:32b:623d:ee91 with SMTP id 98e67ed59e1d1-339a6f36e19mr7456584a91.27.1759397737057; Thu, 02 Oct 2025 02:35:37 -0700 (PDT) Received: from [10.204.101.186] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339a6ff0d4esm4593006a91.17.2025.10.02.02.35.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 02:35:35 -0700 (PDT) Message-ID: <404e40cf-8c51-d12c-d39c-6cc83779e3ca@oss.qualcomm.com> Date: Thu, 2 Oct 2025 15:05:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 5/8] media: iris: Move vpu register defines to common header file Content-Language: en-US To: Konrad Dybcio , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy References: <20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com> <20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OJoqHCaB c=1 sm=1 tr=0 ts=68de476a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=xrcbAuTPtFrA5IWV9RAA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAzMiBTYWx0ZWRfX5ubUlmadDNng JxJm+uCNdXT+mHE8L+hSswcvrtdOxWE018AqozTZcKqmEW3tSwhlb6Xx+AaG1gn4kEruVk3x9Rj uLGDsBWdz+nOMQ0xGq9Pcz+m/0yoe+bOK1QUWlrCUhVQNk7UPJJbIVC7nNIh6m33Fx8tHayQ5Pa OvGdp6G4+uhW3R+/YOgw052aRdthZ6M7HfMC6W1m+tFdZoq3wkIUG+dBlmjavsZnad9LLA2Xl38 urF93lcXMWTSTNLrnoU2hN1aQscFPKeD+YYBPQ2/8zgZ0Jhxodbf/vf5mZZRjhGpAywcCddAi6w ZxlRMNx9liSt0LjvkJt/S382UpI5Eed6BXf49FIDODxgg4pWIv7zocM85C6wSSrB1VtrU18SOcX 0Hlz7wF3bSSt84Q6brkX7KrvW/QSsg== X-Proofpoint-ORIG-GUID: akUplVgr0WohZjmPXgOA3PeYMZrT4gna X-Proofpoint-GUID: akUplVgr0WohZjmPXgOA3PeYMZrT4gna X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-02_03,2025-10-02_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270032 On 9/25/2025 2:40 PM, Konrad Dybcio wrote: > On 9/25/25 1:14 AM, Vikash Garodia wrote: >> Some of vpu4 register defines are common with vpu3x. Move those into the >> common register defines header. This is done to reuse the defines for >> vpu4 in subsequent patch which enables the power sequence for vpu4. >> >> Co-developed-by: Vishnu Reddy >> Signed-off-by: Vishnu Reddy >> Signed-off-by: Vikash Garodia >> --- >> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ---------------------- >> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 -------------- >> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++ > > This is a slippery slope. I think it's better if you explicitly say > the header file contains the register map of VPU3 instead, as let's say > VPU5 may add a random register in the middle (pushing some existing ones > +0x4 down). Such changes are annoying to debug, and we've unfortunately > been there on Adreno.. > > Because you're using this for a single common function that is both acting > upon the same registers and performing the same operations on them across > VPU35 and VPU4, it's okay to de-static-ize the function from iris_vpu3.c and > refer to it from vpu4 ops, keeping the register map private to the former > file which I think will end up less error-prone for the future. Appreciate your thoughts on this and trying to bring the design issues faced in adreno. I peeked into vpu5 register map, and it follows the offsets from vpu4 and should reuse them from "iris_vpu_register_defines.h". IMO, we should be good in reusing them for vpu4 and atleast for next generation. Regards, Vikash