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([2a01:e0a:3d9:2080:fb2e:6266:4e39:ce68]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442ebd6fe86sm184664845e9.0.2025.05.20.01.57.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 May 2025 01:57:06 -0700 (PDT) Message-ID: <405accea-0b4c-4891-9022-425ddc886902@linaro.org> Date: Tue, 20 May 2025 10:57:05 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH 2/2] drm/panel-simple: add AUO P238HAN01 panel entry To: Michael Walle , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Sam Ravnborg Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20250520074439.655749-1-mwalle@kernel.org> <20250520074439.655749-2-mwalle@kernel.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250520074439.655749-2-mwalle@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 20/05/2025 09:44, Michael Walle wrote: > Timings taken from the datasheet and the display is working in DE mode, > thus the datasheet only specifies the blanking period. sync, back porch > and front porch are arbitrarily chosen. > > The datasheet can be found at [1] but for reference these are the > relevant timings: > > sym | | min | typ | max | unit | > ------|--------------+------+------+------+------+ > Tv | V period | 1094 | 1130 | 1836 | Th | > | V active | 1080 | 1080 | 1080 | Th | > | V blanking | 14 | 50 | 756 | Th | > Fv | V frequency | 49 | 60 | 76 | Hz | > Th | H period | 1000 | 1050 | 1678 | Tclk | > | H active | 960 | 960 | 960 | Tclk | > | H blanking | 40 | 90 | 718 | Tclk | > Fh | H frequency | 53.7 | 67.8 | 90.0 | kHz | > Tclk | LVDS clock | 53.7 | 71.2 | 90.0 | MHz | > > Keep in mind that this is a dual link LVDS panel and the horizontal > timings are only for one half of the panel. > > [1] https://www.fortec-integrated.de/fileadmin/pdf/produkte/TFT-Displays/AUO/P238HAN01.0_Datasheet.pdf > > Signed-off-by: Michael Walle > --- > drivers/gpu/drm/panel/panel-simple.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c > index 0a3b26bb4d73..47222d2d8129 100644 > --- a/drivers/gpu/drm/panel/panel-simple.c > +++ b/drivers/gpu/drm/panel/panel-simple.c > @@ -1268,6 +1268,30 @@ static const struct panel_desc auo_g190ean01 = { > .connector_type = DRM_MODE_CONNECTOR_LVDS, > }; > > +static const struct display_timing auo_p238han01_timings = { > + .pixelclock = { 107400000, 142400000, 180000000 }, > + .hactive = { 1920, 1920, 1920 }, > + .hfront_porch = { 30, 70, 650 }, > + .hback_porch = { 30, 70, 650 }, > + .hsync_len = { 20, 40, 136 }, > + .vactive = { 1080, 1080, 1080 }, > + .vfront_porch = { 5, 19, 318 }, > + .vback_porch = { 5, 19, 318 }, > + .vsync_len = { 4, 12, 120 }, > +}; > + > +static const struct panel_desc auo_p238han01 = { > + .timings = &auo_p238han01_timings, > + .num_timings = 1, > + .bpc = 8, > + .size = { > + .width = 527, > + .height = 296, > + }, > + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, > + .connector_type = DRM_MODE_CONNECTOR_LVDS, > +}; > + > static const struct display_timing auo_p320hvn03_timings = { > .pixelclock = { 106000000, 148500000, 164000000 }, > .hactive = { 1920, 1920, 1920 }, > @@ -4938,6 +4962,9 @@ static const struct of_device_id platform_of_match[] = { > }, { > .compatible = "auo,g190ean01", > .data = &auo_g190ean01, > + }, { > + .compatible = "auo,p238han01", > + .data = &auo_p238han01, > }, { > .compatible = "auo,p320hvn03", > .data = &auo_p320hvn03, Reviewed-by: Neil Armstrong