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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506bc8842sm77825665ad.44.2025.06.02.20.17.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Jun 2025 20:17:23 -0700 (PDT) Message-ID: <405f0432-3f07-45be-8511-06235dcd84d0@oss.qualcomm.com> Date: Tue, 3 Jun 2025 11:17:18 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: qcs615: disable the CTI device of the camera block To: Konrad Dybcio , Jie Gan , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Tingwei Zhang , Jinlong Mao , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250527015224.7343-1-jie.gan@oss.qualcomm.com> <5fbb515a-c3d0-4bbe-a689-41e730ecd952@oss.qualcomm.com> <9a156925-cf7b-4d2e-88a8-fdfed5528553@quicinc.com> <1fef810c-47fe-4f6d-95bc-0d72dbd63bf0@oss.qualcomm.com> <79f5e42f-f857-4247-abf9-d0f3f5c1a498@quicinc.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: hdTcMwzATwMPpD9_DfwwN72GspuHYWPm X-Authority-Analysis: v=2.4 cv=EPcG00ZC c=1 sm=1 tr=0 ts=683e6945 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=P-IC7800AAAA:8 a=BXdiI9v_AKGlemzBL5QA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=d3PnA9EDa4IxuAV0gXij:22 X-Proofpoint-GUID: hdTcMwzATwMPpD9_DfwwN72GspuHYWPm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjAzMDAyNyBTYWx0ZWRfX8qQI7aXJgJHr ZE6E7o9KGhpvvtpDAQPtujHt4U3OEJrBYInPpElncaOvalDPoTdseic6QormwRJW4u/aIKEUn81 cuT1ZWNqJNtx80YDfy9vDnnzD4ZeTjNnaPyLLfnB9xS0yaiSFKkatha7HuA+CKCmosqT/QDXh+r SPuHErNC2s/B0j8Hy5quXPgbPtii2eJy9C7J863gz4EYfXSTCdLpX6Vu5vAh4SFuBOjTCwqwT8X Z8/+TkBjYqZAHcUdmWWOQ/Ni6QVTsHnv5HTeXf9Fpv8jYPhmvqK5p8NlGT+gjsy3AtjUUSNC+aP LyECMiLiYlQvQBI/6ustbkMK9SoiLe5mH2w4eOg0hodKdGVgrYCmYg2otaSLcRl1FuXuqieP1ny 43nvUKUBndn0DsoPUGS9fE5U+zbx5qVL80jIPXGvvulOBm7tSlc4O87LIlvNClFtyHZoK1az X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-02_08,2025-06-02_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxscore=0 clxscore=1015 mlxlogscore=841 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506030027 On 5/31/2025 7:05 AM, Konrad Dybcio wrote: > On 5/28/25 5:02 AM, Jie Gan wrote: >> >> >> On 5/27/2025 6:41 PM, Konrad Dybcio wrote: >>> On 5/27/25 12:32 PM, Jie Gan wrote: >>>> >>>> >>>> On 5/27/2025 6:23 PM, Konrad Dybcio wrote: >>>>> On 5/27/25 3:52 AM, Jie Gan wrote: >>>>>> Disable the CTI device of the camera block to prevent potential NoC errors >>>>>> during AMBA bus device matching. >>>>>> >>>>>> The clocks for the Qualcomm Debug Subsystem (QDSS) are managed by aoss_qmp >>>>>> through a mailbox. However, the camera block resides outside the AP domain, >>>>>> meaning its QDSS clock cannot be controlled via aoss_qmp. >>>>> >>>>> Which clock drives it then? >>>> >>>> It's qcom,aoss-qmp. >>>> >>>> clk_prepare->qmp_qdss_clk_prepare >>>> https://elixir.bootlin.com/linux/v6.15-rc7/source/drivers/soc/qcom/qcom_aoss.c#L280 >>> >>> I'm confused about this part: >>> >>>> However, the camera block resides outside the AP domain, >>>> meaning its QDSS clock cannot be controlled via aoss_qmp. >>> >>> Do we need to poke the QMP of another DRV? >> >> The AOSS has a clock control register for all QDSS clocks. when we vote the qdss clock, the aoss_qmp driver will send a message to AOSS to enable the clock control register, then the clock control register will enable all QDSS clocks. >> >> The QDSS clock is not a single clock source, it is a term that representing all the clock sources utilized by the QDSS. > > What I'm trying to ask is, is there any way we could enable that > clock from Linux? Can the camera hw turn these on? Maybe we could > trick it into enabling them? There is a power issue if we keep the debug clock on with a long time. We had a discussion with AOP to check if possible to add the debug clock of titan to the QDSS clock list, but they need time to evaluate it. From Coresight view, what we can do by now is disable it in DT to prevent the unexpected NoC error. Thanks, Jie > > Konrad