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From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Rob Clark" <robdclark@gmail.com>,
	quic_abhinavk@quicinc.com, "Sean Paul" <sean@poorly.run>,
	"Marijn Suijten" <marijn.suijten@somainline.org>,
	"David Airlie" <airlied@gmail.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Simona Vetter" <simona.vetter@ffwll.ch>,
	quic_ebharadw@quicinc.com, linux-arm-msm@vger.kernel.org,
	dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,
	"Rob Clark" <robdclark@chromium.org>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v4 15/25] drm/msm/dpu: Add CWB to msm_display_topology
Date: Fri, 3 Jan 2025 10:03:35 -0800	[thread overview]
Message-ID: <4069bd6a-c37f-4dbe-bbd6-5b333ee54ad8@quicinc.com> (raw)
In-Reply-To: <ki35rornnos35r3fzg5yyqzxnqua3dyfb6ewq2aefrh4u74vfi@opdnf44ntten>



On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 16, 2024 at 04:43:26PM -0800, Jessica Zhang wrote:
>> Add the cwb_enabled flag to msm_display topology and adjust the toplogy
>> to account for concurrent writeback
> 
> Why?

Hi Dmitry,

This flag is necessary to specify that CWB mux(es) need to be assigned 
for the given reqeusted topology.

> 
>>
>> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++++++-
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c   | 10 ++++++++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h   |  2 ++
>>   3 files changed, 20 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index b4bfded3d53025853cee112ca598533ece290318..b063c8fe4c0594772d84401fa56c9c21afc0ad18 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -1198,6 +1198,8 @@ static struct msm_display_topology dpu_crtc_get_topology(
>>   		dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
>>   					    &crtc_state->adjusted_mode);
>>   
>> +	topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state);
>> +
>>   	/*
>>   	 * Datapath topology selection
>>   	 *
>> @@ -1209,9 +1211,16 @@ static struct msm_display_topology dpu_crtc_get_topology(
>>   	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
>>   	 *
>>   	 * Add dspps to the reservation requirements if ctm is requested
>> +	 *
>> +	 * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not
>> +	 * enabled. This is because in cases where CWB is enabled, num_intf will
>> +	 * count both the WB and real-time phys encoders.
>> +	 *
>> +	 * For non-DSC CWB usecases, have the num_lm be decided by the
>> +	 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
>>   	 */
>>   
>> -	if (topology.num_intf == 2)
>> +	if (topology.num_intf == 2 && !topology.cwb_enabled)
>>   		topology.num_lm = 2;
>>   	else if (topology.num_dsc == 2)
>>   		topology.num_lm = 2;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index b763ef19f4c60ae8a35df6a6ffb19e8411bc63f8..85adaf256b2c705d2d7df378b6ffc0e578f52bc3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -382,8 +382,14 @@ static int _dpu_rm_reserve_ctls(
>>   	int i = 0, j, num_ctls;
>>   	bool needs_split_display;
>>   
>> -	/* each hw_intf needs its own hw_ctrl to program its control path */
>> -	num_ctls = top->num_intf;
>> +	/*
>> +	 * For non-CWB mode, each hw_intf needs its own hw_ctl to program its
>> +	 * control path. Hardcode num_ctls to 1 if CWB is enabled
>> +	 */
> 
> Why?

This is because num_intf is based on the number of phys_encs. Since in 
the CWB case, the WB and real-time encoders will be driven by the same 
CTL. I can add this to the comment doc.

Thanks,

Jessica Zhang

> 
>> +	if (top->cwb_enabled)
>> +		num_ctls = 1;
>> +	else
>> +		num_ctls = top->num_intf;
>>   
>>   	needs_split_display = _dpu_rm_needs_split_display(top);
>>   
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index b061dfdab52e04ab7d777e912a30173273cb3db7..12db21a2403ec6930894c36a58e898c5d94c2568 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -46,6 +46,7 @@ struct dpu_rm {
>>    * @num_dspp:     number of dspp blocks used
>>    * @num_dsc:      number of Display Stream Compression (DSC) blocks used
>>    * @needs_cdm:    indicates whether cdm block is needed for this display topology
>> + * @cwb_enabled:  indicates whether CWB is enabled for this display topology
>>    */
>>   struct msm_display_topology {
>>   	u32 num_lm;
>> @@ -53,6 +54,7 @@ struct msm_display_topology {
>>   	u32 num_dspp;
>>   	u32 num_dsc;
>>   	bool needs_cdm;
>> +	bool cwb_enabled;
>>   };
>>   
>>   int dpu_rm_init(struct drm_device *dev,
>>
>> -- 
>> 2.34.1
>>
> 
> -- 
> With best wishes
> Dmitry


  reply	other threads:[~2025-01-03 18:03 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-17  0:43 [PATCH v4 00/25] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 01/25] drm: add clone mode check for CRTC Jessica Zhang
2024-12-17  1:49   ` Abhinav Kumar
2024-12-17 17:16   ` Maxime Ripard
2024-12-17  0:43 ` [PATCH v4 02/25] drm/tests: Add test for drm_crtc_in_clone_mode() Jessica Zhang
2024-12-17  2:06   ` Abhinav Kumar
2024-12-17 17:17   ` Maxime Ripard
2024-12-17  0:43 ` [PATCH v4 03/25] drm: Add valid clones check Jessica Zhang
2024-12-17 17:17   ` Maxime Ripard
2024-12-17  0:43 ` [PATCH v4 04/25] drm/tests: Add test for drm_atomic_helper_check_modeset() Jessica Zhang
2024-12-17 12:14   ` Maxime Ripard
2024-12-17  0:43 ` [PATCH v4 05/25] drm/msm/dpu: get rid of struct dpu_rm_requirements Jessica Zhang
2024-12-17  1:26   ` Dmitry Baryshkov
2024-12-17  2:11     ` Abhinav Kumar
2024-12-17  0:43 ` [PATCH v4 06/25] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Jessica Zhang
2024-12-24  4:45   ` Dmitry Baryshkov
2024-12-24 20:00     ` Dmitry Baryshkov
2025-01-15  5:28       ` Jessica Zhang
2025-01-15  9:56         ` Dmitry Baryshkov
2025-01-16  4:13           ` Jessica Zhang
2025-01-16  7:32             ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 07/25] drm/msm/dpu: move resource allocation to CRTC Jessica Zhang
2024-12-17  1:47   ` Abhinav Kumar
2024-12-20  2:32     ` Dmitry Baryshkov
2024-12-20  2:50       ` Dmitry Baryshkov
2024-12-24  5:02   ` Dmitry Baryshkov
2024-12-26 18:14     ` Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 08/25] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Jessica Zhang
2024-12-17  1:39   ` Abhinav Kumar
2024-12-20  2:40     ` Dmitry Baryshkov
2024-12-20  2:52       ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 09/25] drm/msm/dpu: Add CWB entry to catalog for SM8650 Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 10/25] drm/msm/dpu: Specify dedicated CWB pingpong blocks Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 11/25] drm/msm/dpu: add devcoredumps for cwb registers Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 12/25] drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 13/25] drm/msm/dpu: add CWB support to dpu_hw_wb Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 14/25] drm/msm/dpu: Add RM support for allocating CWB Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 15/25] drm/msm/dpu: Add CWB to msm_display_topology Jessica Zhang
2024-12-20  5:03   ` Dmitry Baryshkov
2025-01-03 18:03     ` Jessica Zhang [this message]
2025-01-03 18:16       ` Dmitry Baryshkov
2025-01-09 22:34         ` Jessica Zhang
2025-01-10  0:00           ` Dmitry Baryshkov
2025-01-10  0:30             ` Jessica Zhang
2025-01-10  1:42               ` Dmitry Baryshkov
2025-01-10  1:50                 ` Jessica Zhang
2025-01-10  2:10                   ` Dmitry Baryshkov
2025-01-10 22:08                     ` Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 16/25] drm/msm/dpu: Require modeset if clone mode status changes Jessica Zhang
2024-12-20  5:41   ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 17/25] drm/msm/dpu: Fail atomic_check if CWB and CDM are enabled Jessica Zhang
2024-12-20  5:44   ` Dmitry Baryshkov
2024-12-26 22:51     ` Jessica Zhang
2024-12-30 23:59       ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 18/25] drm/msm/dpu: Reserve resources for CWB Jessica Zhang
2024-12-20  5:52   ` Dmitry Baryshkov
2024-12-21  0:12     ` Jessica Zhang
2024-12-21  1:07       ` Dmitry Baryshkov
2024-12-26 22:49         ` Jessica Zhang
2024-12-29  4:47           ` Dmitry Baryshkov
2025-01-09 21:26             ` Jessica Zhang
2025-01-09 22:13               ` Dmitry Baryshkov
2025-01-09 22:53                 ` Jessica Zhang
2025-01-10  0:02                   ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 19/25] drm/msm/dpu: Configure CWB in writeback encoder Jessica Zhang
2024-12-20  5:55   ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 20/25] drm/msm/dpu: Support CWB in dpu_hw_ctl Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 21/25] drm/msm/dpu: Adjust writeback phys encoder setup for CWB Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 22/25] drm/msm/dpu: Start frame done timer after encoder kickoff Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 23/25] drm/msm/dpu: Skip trigger flush and start for CWB Jessica Zhang
2024-12-17  0:43 ` [PATCH v4 24/25] drm/msm/dpu: Reorder encoder kickoff " Jessica Zhang
2024-12-20  6:00   ` Dmitry Baryshkov
2024-12-17  0:43 ` [PATCH v4 25/25] drm/msm/dpu: Set possible clones for all encoders Jessica Zhang
2024-12-20  5:11 ` [PATCH v4 00/25] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ Dmitry Baryshkov
2024-12-20 18:46   ` Jessica Zhang
2024-12-24 20:41 ` Dmitry Baryshkov
2025-01-07 23:50 ` (subset) " Dmitry Baryshkov

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