From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6326AC07E9C for ; Wed, 14 Jul 2021 08:41:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 495BE6052B for ; Wed, 14 Jul 2021 08:41:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238617AbhGNIo1 (ORCPT ); Wed, 14 Jul 2021 04:44:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238432AbhGNIo0 (ORCPT ); Wed, 14 Jul 2021 04:44:26 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81F37C06175F; Wed, 14 Jul 2021 01:41:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 9327A1F42ABD Subject: Re: [PATCH 3/6] arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 To: Chun-Kuang Hu Cc: linux-kernel , Jitao Shi , Matthias Brugger , Nicolas Boichat , Eizan Miyamoto , Collabora Kernel ML , "moderated list:ARM/Mediatek SoC support" , Hsin-Yi Wang , Philipp Zabel , Rob Herring , DTML , Linux ARM References: <20210630144646.868702-1-enric.balletbo@collabora.com> <20210630164623.3.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid> From: Enric Balletbo i Serra Message-ID: <406a96c6-8547-1908-0f52-fca783d05262@collabora.com> Date: Wed, 14 Jul 2021 10:41:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Chun-Kuang, Thank you for the review. On 1/7/21 0:48, Chun-Kuang Hu wrote: > HI, Enric: > > Enric Balletbo i Serra 於 2021年6月30日 週三 下午10:47寫道： >> >> Reset the DSI hardware is needed to prevent different settings between >> the bootloader and the kernel. >> >> Signed-off-by: Enric Balletbo i Serra >> --- >> >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ >> include/dt-bindings/reset/mt8173-resets.h | 2 ++ >> 2 files changed, 4 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> index e5596fe01a1d..36c3998eb7f1 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi >> @@ -1036,6 +1036,7 @@ mmsys: syscon@14000000 { >> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; >> assigned-clock-rates = <400000000>; >> #clock-cells = <1>; >> + #reset-cells = <1>; >> mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, >> <&gce 1 CMDQ_THR_PRIO_HIGHEST>; >> mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; >> @@ -1262,6 +1263,7 @@ dsi0: dsi@1401b000 { >> <&mmsys CLK_MM_DSI0_DIGITAL>, >> <&mipi_tx0>; >> clock-names = "engine", "digital", "hs"; >> + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > > Add this in binding document. It would be good if the binding document > is in yaml format. > Ack, will add this optional property in the mediatek,dsi.txt binding. I can try to translate it to yaml but IMO would be better if someone that really knows the hardware and has access to the datasheet could do it. From the current .txt file I can deduce most of the things, but still I can lack some kind of information, i.e I know that there are three clocks, but don't know if all three are needed (from .txt yes, are all needed but not sure), also I know that the names of the clocks are "engine", "digital", and "hs", but I don't know the description of these clocks. IMHO would be nice if someone from Mediatek can take care of all the binding migration to yaml. Cheers, Enric > Regards, > Chun-Kuang. > >> phys = <&mipi_tx0>; >> phy-names = "dphy"; >> status = "disabled"; >> diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h >> index ba8636eda5ae..6a60c7cecc4c 100644 >> --- a/include/dt-bindings/reset/mt8173-resets.h >> +++ b/include/dt-bindings/reset/mt8173-resets.h >> @@ -27,6 +27,8 @@ >> #define MT8173_INFRA_GCE_FAXI_RST 40 >> #define MT8173_INFRA_MMIOMMURST 47 >> >> +/* MMSYS resets */ >> +#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25 >> >> /* PERICFG resets */ >> #define MT8173_PERI_UART0_SW_RST 0 >> -- >> 2.30.2 >>