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Thu, 31 Jul 2025 08:34:36 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56V8YaGN004767 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 31 Jul 2025 08:34:36 GMT Received: from [10.218.4.141] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 31 Jul 2025 01:34:31 -0700 Message-ID: <40ace3bc-7e5d-417a-b51a-148c5f498992@quicinc.com> Date: Thu, 31 Jul 2025 14:04:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Enable MCQ support for UFS controller To: Krzysztof Kozlowski , , , , , , , , , , CC: , , , References: <20250730082229.23475-1-quic_rdwivedi@quicinc.com> <20250730082229.23475-3-quic_rdwivedi@quicinc.com> Content-Language: en-US From: Ram Kumar Dwivedi In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMxMDA1OCBTYWx0ZWRfX3PSo2kA0jfdI j104pu3PEbEv2O7UB8ikFcC7SDFNHvsyHR1URyx9QBBV1JPlOnclQYtIUfKjXi71KlGsQlaY+8C Aju492vgefYdvbM6mxL92DKV7rmdrxmZxnArQqQ7Opy816BQo2Wntecx/qOa87GNOMBO2WHNDuw jRw5d4tZ4kxfiSy1nB2KTOfMsiVBRLEX60GhzgNcEhMBjFTRzegzdKYjaaalaCI0/N+YMmbN6EP jb2fn7vBgTPDAJ//Z9bD24zYUlvcKy1atXbZ/co5yY3VLlArov6iCynq0P3FYuOLAvHoM9l86Dk HJviXwBli9JRdmcFyivQTGytQZsjpZlxwghyD26pHSKDu4uNqEBLZGjla67rP1af0eJWSKaoU/r cMSdiNYxcid0uykTXN4umaPFU9JgBiWGfs6tGm63iL+wEtk7ynwxSGT5MMjCbKAGACe49H7L X-Authority-Analysis: v=2.4 cv=JKw7s9Kb c=1 sm=1 tr=0 ts=688b2a9c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=tmieQKLTGtwJ4DsHDJoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: beaF7mcItC4dzvdkle8yG7bLbbMdBIjS X-Proofpoint-GUID: beaF7mcItC4dzvdkle8yG7bLbbMdBIjS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_01,2025-07-31_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507310058 On 31-Jul-25 12:15 PM, Krzysztof Kozlowski wrote: > On 30/07/2025 10:22, Ram Kumar Dwivedi wrote: >> Enable Multi-Circular Queue (MCQ) support for the UFS host controller >> on the Qualcomm SM8650 platform by updating the device tree node. This >> includes adding new register regions and specifying the MSI parent >> required for MCQ operation. >> >> MCQ is a modern queuing model for UFS that improves performance and >> scalability by allowing multiple hardware queues. >> >> Changes: >> - Add reg entries for mcq_sqd and mcq_vs regions. >> - Define reg-names for the new regions. >> - Specify msi-parent for interrupt routing. >> >> Signed-off-by: Ram Kumar Dwivedi >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index e14d3d778b71..5d164fe511ba 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -3982,7 +3982,12 @@ ufs_mem_phy: phy@1d80000 { >> >> ufs_mem_hc: ufshc@1d84000 { >> compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> - reg = <0 0x01d84000 0 0x3000>; >> + reg = <0 0x01d84000 0 0x3000>, >> + <0 0x01da5000 0 0x2000>, >> + <0 0x01da4000 0 0x0010>; > > > These are wrong address spaces. Open your datasheet and look there. > Hi Krzysztof, I’ve reviewed it again, and it is correct and functioning as expected both on our upstream and downstream codebase. I think it is probably overlooked by you. Can you please double check from your end? Thanks, Ram. > > Best regards, > Krzysztof