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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3b778eb284fsm3718859f8f.12.2025.07.26.12.37.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Jul 2025 12:37:44 -0700 (PDT) Message-ID: <4101aa1a-efa3-418b-aa96-0157ffc7198f@linaro.org> Date: Sat, 26 Jul 2025 21:37:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/20] clocksource/drivers/vf-pit: Register the clocksource from the driver To: Ghennadi Procopciuc , tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org References: <20250705160129.3688026-1-daniel.lezcano@linaro.org> <20250705160129.3688026-9-daniel.lezcano@linaro.org> <86dd0130-b9bc-46cd-9bbd-033eafbbd5e0@oss.nxp.com> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <86dd0130-b9bc-46cd-9bbd-033eafbbd5e0@oss.nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 07/07/2025 14:02, Ghennadi Procopciuc wrote: > On 7/5/2025 7:01 PM, Daniel Lezcano wrote: > [...] > >> +static u64 pit_timer_clocksource_read(struct clocksource *cs) >> +{ >> + struct pit_timer *pit = cs_to_pit(cs); >> + >> + return ~(u64)readl(pit->clksrc_base + PITCVAL); >> +} > > The CVAL register is a 32-bit countdown timer. Casting its value to 64 bits before applying bitwise negation results in a 64-bit value where the upper 32 bits are always set. To avoid this, shouldn't the operations be reordered so that the bitwise negation is applied first to the 32-bit value, followed by casting the result to 64 bits? > Yes, that's right Good catch ! Thanks -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog