Re: [PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs

[Stephen Boyd <sboyd@kernel.org>]

Quoting Sergio Paracuellos (2024-09-09 21:40:23)
> Base clocks are the first in being probed and are real dependencies of the
> rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880,
> RT305x and RT3883 'xtal' must be defined first since in any other case,
> when fixed clocks are probed they are delayed until 'xtal' is probed so the
> following warning appears:
> 
>  WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138
>  Modules linked in:
>  CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0
>  Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000
>  80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000
>  00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000
>  203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009
>  00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000
>  ...
>  Call Trace:
>  [<800065d0>] show_stack+0x64/0xf4
>  [<804bca14>] dump_stack_lvl+0x38/0x60
>  [<800218ac>] __warn+0x94/0xe4
>  [<8002195c>] warn_slowpath_fmt+0x60/0x94
>  [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138
>  [<80254530>] __clk_register+0x568/0x688
>  [<80254838>] of_clk_hw_register+0x18/0x2c
>  [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594
>  [<8070b628>] of_clk_init+0x1c0/0x23c
>  [<806fc448>] plat_time_init+0x58/0x18c
>  [<806fdaf0>] time_init+0x10/0x6c
>  [<806f9bc4>] start_kernel+0x458/0x67c
> 
>  ---[ end trace 0000000000000000 ]---

Applied to clk-next