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Wed, 16 Aug 2023 15:08:00 GMT Received: from [10.216.9.49] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 16 Aug 2023 08:07:54 -0700 Message-ID: <41151f25-4622-f906-06a2-e8cd65e4b211@quicinc.com> Date: Wed, 16 Aug 2023 20:37:47 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , , Andy Gross , "Bjorn Andersson" , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1692192264-18515-1-git-send-email-quic_krichai@quicinc.com> <1692192264-18515-3-git-send-email-quic_krichai@quicinc.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 31cLl94Ge3nJhP_GQHox_prnPM6hwlO2 X-Proofpoint-ORIG-GUID: 31cLl94Ge3nJhP_GQHox_prnPM6hwlO2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-16_15,2023-08-15_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308160131 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/16/2023 7:10 PM, Dmitry Baryshkov wrote: > On Wed, 16 Aug 2023 at 16:25, Krishna chaitanya chundru > wrote: >> PCIe needs to choose the appropriate performance state of RPMH power >> domain based upon the PCIe gen speed. >> >> So let's add the OPP table support to specify RPMH performance states. >> >> Signed-off-by: Krishna chaitanya chundru >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 595533a..c77a683 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -1803,7 +1803,28 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie0_default_state>; >> >> + operating-points-v2 = <&pcie0_opp_table>; >> + >> status = "disabled"; >> + >> + pcie0_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { > As a random suggestion: these frequencies are calculated by the > driver. It might be easier to use opp-level for the PCIe generation > instead. > > This way this OPP entry can become: > > opp-1 { > opp-level = <1>; > required-opps = <&rpmhpd_opp_low_svs>; > }; This looks good I will try to do in this approach in the next patch if there are no other comments. - KC > >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie0_phy: phy@1c06000 { >> @@ -1915,7 +1936,33 @@ >> pinctrl-names = "default"; >> pinctrl-0 = <&pcie1_default_state>; >> >> + operating-points-v2 = <&pcie1_opp_table>; >> + >> status = "disabled"; >> + >> + pcie1_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-16000000 { >> + opp-hz = /bits/ 64 <16000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> }; >> >> pcie1_phy: phy@1c0f000 { >> -- >> 2.7.4 >> >