Re: [PATCH 5/5] x86/feature: Detect the x86 feature Indirect Branch Prediction Barrier

[Tom Lendacky <thomas.lendacky@amd.com>]

On 1/12/2018 9:36 AM, Woodhouse, David wrote:
> On Fri, 2018-01-12 at 09:31 -0600, Tom Lendacky wrote:
>>
>> AMD will follow the specification that if cpuid ax=0x7, return rdx[26]
>> is set, it will indicate both MSR registers and features are supported.
>>
>> But AMD also has a separate bit for IBPB (X86_FEATURE_PRED_CMD) alone.
>> As all of the IBRS/IBPB stuff happens, that patch will follow.
> 
> Please let's roll it into the patch set. I don't want Intel posting
> deliberately AMD-ignoring patches. Sort it out, guys.
> 

Based on the current patches, here is what it should be for the
standalone IBPB support:

x86/cpu: Detect standalone IBPB support

From: Tom Lendacky <thomas.lendacky@amd.com>

Add support to detect standalone IBPB feature support.  This feature is
indicated as follows:

  CPUID EAX=0x80000008, ECX=0x00 return EBX[12] indicates support for
  IBPB

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 arch/x86/include/asm/cpufeatures.h |    1 +
 arch/x86/kernel/cpu/spec_ctrl.c    |    9 +++++----
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 52f37fc..33f0215 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -273,6 +273,7 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
diff --git a/arch/x86/kernel/cpu/spec_ctrl.c b/arch/x86/kernel/cpu/spec_ctrl.c
index 6cfec19..1aadd73 100644
--- a/arch/x86/kernel/cpu/spec_ctrl.c
+++ b/arch/x86/kernel/cpu/spec_ctrl.c
@@ -16,12 +16,13 @@ void spec_ctrl_scan_feature(struct cpuinfo_x86 *c)
 				static_branch_enable(&spec_ctrl_dynamic_ibrs);
 		}
 		/*
-		 * For Intel CPU's this MSR is shared the same cpuid
-		 * enumeration. When MSR_IA32_SPEC_CTRL is present
-		 * MSR_IA32_SPEC_CTRL is also available
-		 * TBD: AMD might have a separate enumeration for each.
+		 * The PRED_CMD MSR is shared with the cpuid enumeration
+		 * for SPEC_CTRL.  When MSR_IA32_SPEC_CTRL is present,
+		 * then MSR_IA32_PRED_CMD is, too.
 		 */
 		set_cpu_cap(c, X86_FEATURE_PRED_CMD);
+	} else if (boot_cpu_has(X86_FEATURE_IBPB)) {
+		set_cpu_cap(c, X86_FEATURE_PRED_CMD);
 	}
 }
 


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