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Thu, 5 Oct 2023 13:56:09 GMT Received: from [10.216.12.172] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 06:56:04 -0700 Message-ID: <416692f7-ffeb-419b-9a05-24909ab13de9@quicinc.com> Date: Thu, 5 Oct 2023 19:25:59 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller Content-Language: en-US From: Kathiravan Thirumoorthy To: Robert Marko , , , , , , , , , References: <20231004191303.331055-1-robimarko@gmail.com> <6dcb61f6-9be4-4feb-a7dd-44d606fcc480@quicinc.com> In-Reply-To: <6dcb61f6-9be4-4feb-a7dd-44d606fcc480@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hGgLs-_VgMRTSWpTO1lae4jKgHpvkrLA X-Proofpoint-ORIG-GUID: hGgLs-_VgMRTSWpTO1lae4jKgHpvkrLA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_08,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=991 malwarescore=0 bulkscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050108 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/5/2023 7:18 PM, Kathiravan Thirumoorthy wrote: > > On 10/5/2023 12:42 AM, Robert Marko wrote: >> Add the required BAM and QUP nodes for the QUP1 SPI controller on >> IPQ5018. >> >> Signed-off-by: Robert Marko >> --- >>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ >>   1 file changed, 24 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> index 38ffdc3cbdcd..484034e65f4f 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi >> @@ -146,6 +146,16 @@ sdhc_1: mmc@7804000 { >>               status = "disabled"; >>           }; >>   +        blsp_dma: dma-controller@7884000 { >> +            compatible = "qcom,bam-v1.7.0"; >> +            reg = <0x07884000 0x1d000>; >> +            interrupts = ; >> +            clocks = <&gcc GCC_BLSP1_AHB_CLK>; >> +            clock-names = "bam_clk"; >> +            #dma-cells = <1>; >> +            qcom,ee = <0>; >> +        }; >> + >>           blsp1_uart1: serial@78af000 { >>               compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; >>               reg = <0x078af000 0x200>; >> @@ -156,6 +166,20 @@ blsp1_uart1: serial@78af000 { >>               status = "disabled"; >>           }; >>   +        blsp1_spi1: spi@78b5000 { >> +            compatible = "qcom,spi-qup-v2.2.1"; >> +            #address-cells = <1>; >> +            #size-cells = <0>; >> +            reg = <0x78b5000 0x600>; > > > Please pad the address part to 8 hex digits with leading zeroes. With > that, > > Reviewed-by: Kathiravan T Once again, missed to spell out last name... Reviewed-by: Kathiravan Thirumoorthy > > >> +            interrupts = ; >> +            clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, >> +                 <&gcc GCC_BLSP1_AHB_CLK>; >> +            clock-names = "core", "iface"; >> +            dmas = <&blsp_dma 4>, <&blsp_dma 5>; >> +            dma-names = "tx", "rx"; >> +            status = "disabled"; >> +        }; >> + >>           intc: interrupt-controller@b000000 { >>               compatible = "qcom,msm-qgic2"; >>               reg = <0x0b000000 0x1000>,  /* GICD */