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Mon, 05 Dec 2022 13:24:08 -0800 (PST) Received: from [127.0.0.1] ([94.25.229.129]) by smtp.gmail.com with ESMTPSA id u17-20020a05651c131100b00279f213302bsm678020lja.57.2022.12.05.13.24.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Dec 2022 13:24:07 -0800 (PST) Date: Tue, 06 Dec 2022 00:23:59 +0300 From: Dmitry Baryshkov To: Bjorn Andersson CC: Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Kalyan Thota , Jessica Zhang , Kuogee Hsieh , Johan Hovold , Sankeerth Billakanti , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 12/13] arm64: dts: qcom: sc8280xp-crd: Enable EDP User-Agent: K-9 Mail for Android In-Reply-To: <20221205174433.16847-13-quic_bjorande@quicinc.com> References: <20221205174433.16847-1-quic_bjorande@quicinc.com> <20221205174433.16847-13-quic_bjorande@quicinc.com> Message-ID: <419ABEAD-3E80-4A6D-AE44-8DF30C4CBA71@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5 December 2022 20:44:32 GMT+03:00, Bjorn Andersson wrote: >From: Bjorn Andersson > >The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes >and link it together with the backlight control=2E > >Signed-off-by: Bjorn Andersson >Signed-off-by: Bjorn Andersson >--- > >Changes since v3: >- Added description of the regulator that powers the panel=2E > > arch/arm64/boot/dts/qcom/sc8280xp-crd=2Edts | 72 ++++++++++++++++++++++- > 1 file changed, 71 insertions(+), 1 deletion(-) > >diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd=2Edts b/arch/arm64/boo= t/dts/qcom/sc8280xp-crd=2Edts >index f09810e3d956=2E=2Ea7d2384cbbe8 100644 >--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd=2Edts >+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd=2Edts >@@ -20,7 +20,7 @@ aliases { > serial0 =3D &qup2_uart17; > }; >=20 >- backlight { >+ backlight: backlight { > compatible =3D "pwm-backlight"; > pwms =3D <&pmc8280c_lpg 3 1000000>; > enable-gpios =3D <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; >@@ -34,6 +34,22 @@ chosen { > stdout-path =3D "serial0:115200n8"; > }; >=20 >+ vreg_edp_3p3: regulator-edp-3p3 { >+ compatible =3D "regulator-fixed"; >+ >+ regulator-name =3D "VREG_EDP_3P3"; >+ regulator-min-microvolt =3D <3300000>; >+ regulator-max-microvolt =3D <3300000>; >+ >+ gpio =3D <&tlmm 25 GPIO_ACTIVE_HIGH>; >+ enable-active-high; >+ >+ pinctrl-names =3D "default"; >+ pinctrl-0 =3D <&edp_reg_en>; >+ >+ regulator-boot-on; >+ }; >+ > vreg_edp_bl: regulator-edp-bl { > compatible =3D "regulator-fixed"; >=20 >@@ -230,6 +246,54 @@ vreg_l9d: ldo9 { > }; > }; >=20 >+&dispcc0 { >+ status =3D "okay"; >+}; >+ >+&mdss0 { >+ status =3D "okay"; >+}; >+ >+&mdss0_dp3 { >+ compatible =3D "qcom,sc8280xp-edp"; >+ status =3D "okay"; >+ >+ data-lanes =3D <0 1 2 3>; >+ >+ aux-bus { >+ panel { >+ compatible =3D "edp-panel"; >+ power-supply =3D <&vreg_edp_3p3>; >+ >+ backlight =3D <&backlight>; >+ >+ ports { >+ port { >+ edp_panel_in: endpoint { >+ remote-endpoint =3D <&mdss0_dp3_out>; >+ }; >+ }; >+ }; >+ }; >+ }; >+ >+ ports { >+ port@1 { >+ reg =3D <1>; You already have reg assignment in the SoC dtsi=2E >+ mdss0_dp3_out: endpoint { >+ remote-endpoint =3D <&edp_panel_in>; >+ }; >+ }; >+ }; >+}; >+ >+&mdss0_dp3_phy { >+ status =3D "okay"; >+ >+ vdda-phy-supply =3D <&vreg_l6b>; >+ vdda-pll-supply =3D <&vreg_l3b>; >+}; >+ > &pcie2a { > perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; > wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; >@@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state { > &tlmm { > gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; >=20 >+ edp_reg_en: edp-reg-en-state { >+ pins =3D "gpio25"; >+ function =3D "gpio"; >+ output-enable; >+ }; >+ > kybd_default: kybd-default-state { > disable-pins { > pins =3D "gpio102"; --=20 With best wishes Dmitry