From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A709BC433EF for ; Mon, 14 Feb 2022 02:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239272AbiBNCzO (ORCPT ); Sun, 13 Feb 2022 21:55:14 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:39768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbiBNCzM (ORCPT ); Sun, 13 Feb 2022 21:55:12 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E40675047A for ; Sun, 13 Feb 2022 18:55:04 -0800 (PST) X-UUID: 2f04974a58114436965ecff49d179511-20220214 X-UUID: 2f04974a58114436965ecff49d179511-20220214 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1369098208; Mon, 14 Feb 2022 10:54:57 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Feb 2022 10:54:56 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Feb 2022 10:54:56 +0800 Message-ID: <41af2aa3b3a39d32e409ec355e59c5f8b1e47f43.camel@mediatek.com> Subject: Re: [1/3] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: CK Hu To: , , , , , CC: , , , , , , Jitao Shi Date: Mon, 14 Feb 2022 10:54:56 +0800 In-Reply-To: <1644589818-13066-2-git-send-email-xinlei.lee@mediatek.com> References: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> <1644589818-13066-2-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Xinlei: On Fri, 2022-02-11 at 22:30 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > In order to cooperate with patch 3/3 modification,it is necessary to > adjust > the position where mipi pulls up the signal. After the patch is applied, the series index (3/3) is disappear, so do not reference series index in commit description. I think this series is to adjust the calling sequence, so you could describe as below: Old sequence: 1. aaa 2. bbb 3. ccc 4. ddd New sequence: 1. bbb 2. aaa 3. ddd 4. ccc and this patch is to adjust 'aaa' and 'bbb'. Regards, CK > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 5d90d2eb..6d7b66d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0);