From: Robin Murphy <robin.murphy@arm.com>
To: Will Deacon <will@kernel.org>, Rob Clark <robdclark@gmail.com>
Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Rob Clark <robdclark@chromium.org>,
Joerg Roedel <joro@8bytes.org>,
"moderated list:ARM SMMU DRIVERS"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] iommu/arm-smmu-qcom: Only enable stall on smmu-v2
Date: Thu, 19 Dec 2024 12:08:39 +0000 [thread overview]
Message-ID: <41d93dac-4ef1-4cc7-a7b2-24c8289f905f@arm.com> (raw)
In-Reply-To: <20241219113019.GA23640@willie-the-truck>
On 2024-12-19 11:30 am, Will Deacon wrote:
> On Mon, Dec 16, 2024 at 09:10:17AM -0800, Rob Clark wrote:
>> From: Rob Clark <robdclark@chromium.org>
>>
>> On mmu-500, stall-on-fault seems to stall all context banks, causing the
>> GMU to misbehave. So limit this feature to smmu-v2 for now.
>
> MMU-500 has public documentation so please can you dig up what the
> actual behaviour is rather than guess?
Yeah, I'm pretty sure that's not true as stated, especially with
SCTLR.HUPCF set as qcom_adreno_smmu_write_sctlr() does. However it is
plausible that at the system interconnect level, a sufficient number of
stalled transactions might backpressure other transactions from entering
the same TBU, even if they are destined for a different context. That's
more about the configuration and integration of individual SoCs than the
SMMU IP used.
Robin.
>> This fixes an issue with an older mesa bug taking outo the system
>> because of GMU going off into the year.
>
> Sorry, but I don't understand this sentence.
>
> Will
next prev parent reply other threads:[~2024-12-19 12:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-16 17:10 Rob Clark
2024-12-16 20:28 ` Akhil P Oommen
2024-12-16 20:54 ` Rob Clark
2024-12-19 11:30 ` Will Deacon
2024-12-19 12:08 ` Robin Murphy [this message]
2024-12-19 15:00 ` Rob Clark
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