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X-CSE-ConnectionGUID: 2hFn1oRYRFyekPcUbDaIiw== X-CSE-MsgGUID: VwCiOMYgTpqP4heFiMPmSA== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="38862944" X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="38862944" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2024 01:16:02 -0700 X-CSE-ConnectionGUID: q92lhPNHSi6TgbaNzQAFJw== X-CSE-MsgGUID: 0YHglm/SSNGUlYQN5X2tdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,275,1716274800"; d="scan'208";a="95015828" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.124.229.145]) ([10.124.229.145]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2024 01:16:00 -0700 Message-ID: <41eda769-f1cf-4e96-9cf7-d74d4802eaf5@linux.intel.com> Date: Fri, 9 Aug 2024 16:15:58 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: baolu.lu@linux.intel.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/5] iommu/vt-d: Introduce interfaces for QI batching operations To: Tina Zhang , Kevin Tian References: <20240809025431.14605-1-tina.zhang@intel.com> <20240809025431.14605-4-tina.zhang@intel.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <20240809025431.14605-4-tina.zhang@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2024/8/9 10:54, Tina Zhang wrote: > Introduces qi_batch_xxx() interfaces to the VT-d driver to enhance the > efficiency of IOTLB and Dev-IOTLB invalidation command processing. > By allowing these commands to be batched together before submission, > the patch aims to minimize the overhead previously incurred when > handling these operations individually. > > The addition of qi_batch_add_xxx() functions enable the accumulation of > invalidation commands into a batch, while the qi_batch_flush_descs() > function allows for the collective submission of these commands. > > Signed-off-by: Tina Zhang > --- > drivers/iommu/intel/dmar.c | 78 +++++++++++++++++++++++++++++++++++++ > drivers/iommu/intel/iommu.h | 39 +++++++++++++++++++ > 2 files changed, 117 insertions(+) > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > index 64724af1a618..8d55c49382fc 100644 > --- a/drivers/iommu/intel/dmar.c > +++ b/drivers/iommu/intel/dmar.c > @@ -1636,6 +1636,84 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, > qi_submit_sync(iommu, &desc, 1, 0); > } > > +static void qi_batch_increment_index(struct intel_iommu *iommu, > + struct qi_batch *batch) > +{ > + if (++batch->index == QI_MAX_BATCHED_DESC_COUNT) > + qi_batch_flush_descs(iommu, batch); > +} > + > +void qi_batch_flush_descs(struct intel_iommu *iommu, struct qi_batch *batch) > +{ > + if (!batch->index) > + return; > + > + qi_submit_sync(iommu, batch->descs, batch->index, 0); > + > + /* Reset the index value and clean the whole batch buffer */ > + memset(batch, 0, sizeof(struct qi_batch)); > +} > + > +void qi_batch_add_iotlb_desc(struct intel_iommu *iommu, u16 did, u64 addr, > + unsigned int size_order, u64 type, > + struct qi_batch *batch) > +{ > + qi_desc_iotlb(iommu, did, addr, size_order, type, &(batch->descs[batch->index])); > + qi_batch_increment_index(iommu, batch); > +} > + > +void qi_batch_add_dev_iotlb_desc(struct intel_iommu *iommu, u16 sid, > + u16 pfsid, u16 qdep, u64 addr, > + unsigned int mask, > + struct qi_batch *batch) > +{ > + /* > + * According to VT-d spec, software is recommended to not submit any Device-TLB > + * invalidation requests while address remapping hardware is disabled. > + */ > + if (!(iommu->gcmd & DMA_GCMD_TE)) > + return; > + > + qi_desc_dev_iotlb(sid, pfsid, qdep, addr, mask, &(batch->descs[batch->index])); > + qi_batch_increment_index(iommu, batch); > +} > + > +void qi_batch_add_piotlb_desc(struct intel_iommu *iommu, u16 did, > + u32 pasid, u64 addr, > + unsigned long npages, bool ih, > + struct qi_batch *batch) > +{ > + /* > + * npages == -1 means a PASID-selective invalidation, otherwise, > + * a positive value for Page-selective-within-PASID invalidation. > + * 0 is not a valid input. > + */ > + if (!npages) > + return; > + > + qi_desc_piotlb(did, pasid, addr, npages, ih, &(batch->descs[batch->index])); > + qi_batch_increment_index(iommu, batch); > +} > + > +void qi_batch_add_dev_iotlb_pasid_desc(struct intel_iommu *iommu, > + u16 sid, u16 pfsid, > + u32 pasid, u16 qdep, > + u64 addr, unsigned int size_order, > + struct qi_batch *batch) > +{ > + /* > + * According to VT-d spec, software is recommended to not submit any Device-TLB > + * invalidation requests while address remapping hardware is disabled. > + */ > + if (!(iommu->gcmd & DMA_GCMD_TE)) > + return; > + > + qi_desc_dev_iotlb_pasid(sid, pfsid, pasid, > + qdep, addr, size_order, > + &(batch->descs[batch->index])); > + qi_batch_increment_index(iommu, batch); > +} How about moving all these helpers into drivers/iommu/intel/cache.c? It's the only consumer for these helpers, right? Thanks, baolu