From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E307C3A5A2 for ; Fri, 23 Aug 2019 05:28:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 287132166E for ; Fri, 23 Aug 2019 05:28:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392101AbfHWF2z (ORCPT ); Fri, 23 Aug 2019 01:28:55 -0400 Received: from mga14.intel.com ([192.55.52.115]:42091 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392067AbfHWF2y (ORCPT ); Fri, 23 Aug 2019 01:28:54 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Aug 2019 22:28:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,420,1559545200"; d="scan'208";a="180596997" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga007.fm.intel.com with ESMTP; 22 Aug 2019 22:28:51 -0700 From: Dilip Kota To: robh@kernel.org, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, Dilip Kota Subject: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller Date: Fri, 23 Aug 2019 13:28:34 +0800 Message-Id: <42039170811f798b8edc66bf85166aefe7dbc903.1566531960.git.eswara.kota@linux.intel.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add YAML schemas for the reset controller on Intel Lightening Mountain (LGM) SoC. Signed-off-by: Dilip Kota --- Changes on v2: Address review comments Update the compatible property definition Add description for reset-cells Add 'additionalProperties: false' property .../bindings/reset/intel,syscon-reset.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml new file mode 100644 index 000000000000..3403a967190a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/intel,syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightening Mountain SoC System Reset Controller + +maintainers: + - Dilip Kota + +properties: + compatible: + items: + - const: intel,rcu-lgm + - const: syscon + + reg: + description: Reset controller register base address and size + + intel,global-reset: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Global reset register offset and bit offset. + + "#reset-cells": + const: 2 + description: | + The 1st cell is the register offset. + The 2nd cell is the bit offset in the register. + +required: + - compatible + - reg + - intel,global-reset + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rcu0: reset-controller@00000000 { + compatible = "intel,rcu-lgm", "syscon"; + reg = <0x000000 0x80000>; + intel,global-reset = <0x10 30>; + #reset-cells = <2>; + }; + + pcie_phy0: pciephy@... { + ... + /* address offset: 0x10, bit offset: 12 */ + resets = <&rcu0 0x10 12>; + ... + }; -- 2.11.0