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([2600:8803:e7e4:500:90d7:b13f:c53:8ca3]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-422eb42db1bsm12915687fac.17.2026.04.06.06.44.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Apr 2026 06:44:06 -0700 (PDT) Message-ID: <420dba4a-0c31-47bc-b84a-5d29702b115e@baylibre.com> Date: Mon, 6 Apr 2026 08:44:05 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 4/4] iio: adc: ad4691: add SPI offload support To: "Sabau, Radu bogdan" , Lars-Peter Clausen , "Hennerich, Michael" , Jonathan Cameron , "Sa, Nuno" , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , Jonathan Corbet , Shuah Khan Cc: "linux-iio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-doc@vger.kernel.org" References: <20260403-ad4692-multichannel-sar-adc-driver-v6-0-fa2a01a57c4e@analog.com> <20260403-ad4692-multichannel-sar-adc-driver-v6-4-fa2a01a57c4e@analog.com> <1d0d41c8-7867-4459-a91a-a2c6774b1885@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/6/26 4:34 AM, Sabau, Radu bogdan wrote: >> -----Original Message----- >> From: David Lechner >> Sent: Saturday, April 4, 2026 6:34 PM > > ... > >>> +Selected when a ``pwms`` property is present in the device tree. The PWM >> drives >>> +the CNV pin independently of SPI at the configured conversion rate, and a >> GP >>> +pin (identified by ``interrupt-names``) asserts DATA_READY at end-of-burst >> to >>> +signal that the AVG_IN result registers are ready to be read. >>> + >>> +The IRQ handler stops the PWM, fires the IIO trigger, and the trigger >> handler >> >> If we stop the PWM after an IRQ, then we don't get a consistent sample rate. >> Ideally, we would leave the PWM running and just pick a rate slow enough >> that >> there is plenty of time to read the data. Otherwise, this mode doesn't seem >> particularly useful. > > Should there also be a condition when setting the sampling frequency, that will > protect from setting too fast sample rates? I haven't figured out a good way to do this since the real max rate depends on a lot of different things and when not using offloading, the time it takes to do SPI xfers is non-deterministic. >>> +IIO DMA buffer: >>> + >>> +* **CNV Burst offload**: the SPI engine reads AVG_IN registers with a 2- >> byte >>> + address phase followed by a 2-byte data phase; the 16-bit result lands in >>> + the lower half of the 32-bit word (``shift=0``). >>> +* **Manual offload**: each 32-bit SPI word carries the channel byte in the >>> + first byte; the 16-bit result is returned in the upper half of the 32-bit >> >> I would expect the "first" byte to be in the "upper half" of the 32-bits as >> well. This layout could be explained better. >> >> Also, since extra data has to be read in this mode, does this affect the max >> conversion rate? > > This is bad documentation on my part. "channel byte" isn't used anymore, > this is previous version behaviour. Right now, only 16-bits worth of actual > channel data are used. > Then why do we need the shift if there is no other data? Can't we rework the SPI message so that there is no shift?