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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3e3bc39d959sm353055b6e.41.2024.10.03.06.08.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Oct 2024 06:08:57 -0700 (PDT) Message-ID: <42165d2b-1103-4316-841c-45514a626be7@baylibre.com> Date: Thu, 3 Oct 2024 08:08:55 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/7] iio: adc: ad485x: add ad485x driver To: "Miclaus, Antoniu" , Andy Shevchenko Cc: Jonathan Cameron , Lars-Peter Clausen , "Hennerich, Michael" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Sa, Nuno" , Olivier Moysan , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , "Schmitt, Marcelo" , =?UTF-8?Q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= , Mike Looijmans , Dumitru Ceclan , AngeloGioacchino Del Regno , Alisa-Dariana Roman , "Cuciurean, Sergiu" , "Bogdan, Dragos" , "linux-iio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-pwm@vger.kernel.org" References: <20240923101206.3753-1-antoniu.miclaus@analog.com> <20240923101206.3753-7-antoniu.miclaus@analog.com> <20240928184722.314b329b@jic23-huawei> <4ee001d2-67d0-45ab-ae62-ce5b8dd7553e@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/3/24 5:14 AM, Miclaus, Antoniu wrote: >> On 10/1/24 8:51 AM, Miclaus, Antoniu wrote: >>>>> Regarding the bulk writes/reads, the msb/mid/lsb registers need to be >>>>> read/write in a specific order and the addresses are not incremental, >>>> >>>> We have _noinc() variants of regmap accessors. >>> [Miclaus, Antoniu] >>> I think _noinc() functions read from the same register address so it doesn't >>> apply. >>> I am reading values from multiple register addresses that are not reg_addr, >>> reg_addr+1, reg_addr+2. >> >> I'm confused by the statement that the registers are not incremental. >> >> For example, this patch defines... >> >> +#define AD485X_REG_CHX_OFFSET_LSB(ch) >> AD485X_REG_CHX_OFFSET(ch) >> +#define AD485X_REG_CHX_OFFSET_MID(ch) >> (AD485X_REG_CHX_OFFSET_LSB(ch) + 0x01) >> +#define AD485X_REG_CHX_OFFSET_MSB(ch) >> (AD485X_REG_CHX_OFFSET_MID(ch) + 0x01) >> >> This looks exactly like reg_addr, reg_addr+1, reg_addr+2 to me. > Yes you are right. Although I tested with hardware and it seems that the registers > are not properly written when using bulk operations. My guess is that holding CS low during > the entire transaction might be a possible issue. Any suggestions are appreciated. Is ADDR_DIR in SPI_CONFIG_A set to the correct value to match how the regmap is configured for bulk writes? I had to set this bit for AD4695 which has a similar register map (although on that one I used two regmaps, an 8-bit one and a 16-bit one, instead of doing bulk operations on the 8-bit one). > >>> >>>>> so I am not sure how the bulk functions fit. On this matter, we will need >>>>> unsigned int (not u8) to store the values read via regmap_read, and in this >>>>> case we will need extra casts and assignments to use get_unaligned. >>>> >>>> -- >>>> With Best Regards, >>>> Andy Shevchenko >>>> >>> >