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d=adamthiede.com; s=MBO0001; t=1781816794; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:autocrypt:autocrypt; bh=wBQkNjECV6xY2iyUaF8p4ty+DWlCLVOGQLFUXgO2Ou4=; b=1o2eMq7CpiT82lLfa/EJ2bHxFGd9w1DrgDAhipxOxOToKoH5b6R6Exfos4jx3OiiFM7szl O3pXAeC2FF7dMTnguh/ngM8RXbAnRCu3X+fjoAP977qNzCafGtvBJvs8YcTt118kkTHnMB uUilaRaKfr5LQ/fIxRUh5mqtsig91nSnsvQa0rNx43GWR3HVa7vVmScKZYZ/3qljYRhSU9 4tY78sF1ojmAjfASV+j0xcVW8E9vB/XcYWckCHHPON9vK4V+t40RvtxZskPNO2l4DdoI+7 hNpS0611k6APoQGAALNp0qSH/OILLRjqJlanB1Wlr7d/i3lb64ZCDWC4VIbhhA== Message-ID: <42607fa4-485d-4142-b31c-7bfac71118d2@adamthiede.com> Date: Thu, 18 Jun 2026 16:06:28 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable To: Gary Bisson , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> Content-Language: en-US From: Adam Thiede Autocrypt: addr=me@adamthiede.com; keydata= xsBNBF+n+90BCAC2ZRLVcvdXDgfY7EppN05eNor3U7/eeiNCCEIWZkYLhikUEP1ReLGBkXpK Pc70hfnKAKkCoth3IwhDty9WXMNU+iLNei4ieb2luW+UqluR6xIUIA+txahMU9YcjVaQTKf/ yZWO4yl6pfBPCxC2UdPZKBAdGoi5NnE0ABFNbhBETQhhBic533lZn33ByupfI3acECnQdjgQ llCUpDbw4I+S/N1iFiEHcbMXH7ZB00e3IYNorZ1E9v7p++5rDY1fQ9gXpieg1vFKwSq1NJWo 9xx336YjaTUbX0EwrdKd9l8AktA3yRjckaK5TAcwSQaDtHvhpbl4ebvPhtwHh699MroXABEB AAHNH0FkYW0gVGhpZWRlIDxtZUBhZGFtdGhpZWRlLmNvbT7CwI4EEwEIADgCGwMFCwkIBwIG FQoJCAsCBBYCAwECHgECF4AWIQQtG9pGQ7sz3tf8M/kC7fV9o/vRzgUCZL1HxQAKCRAC7fV9 o/vRzgyRB/wLqRCvvWhQCMgvzeKvru9wcXquhb77K8H/ByLbfiT8YBuP3lZFVh0IQhgO9Ylk fIoOJE4V+jjxyOnO2d9xjGbvAmmR6yT0gfLzSVWqrC4k+V9MWLv43nrNzxt41dvo5j824FAl X+zaiRZCdO8Jtxg5Elpiop2SKLi1utX1Z8i6YZh+ccJZlchUBAGUTk+D4UjK7vUcjLWT96ya CtdtTfXyw36CvGOPEWfc6++Kkl/5sgej1i7biPYzu/r0vssaQYTXKSrv6Cfa3Maa89ASiTtv q4qmhLnJeCrPxWlRAf6LEizeBEkOasYni2u8sp4wBezEq45Ozu45sfPkqLpPolG7zsBNBF+n +90BCADBRt+vrToRBEG580n77S99qSEkbKD+oJtCVyovnjMNkg0K9UG68LIeCX/ezngiV1M8 JISvw5iFOuUFqGX/1hLl9wgt/YpuIrgWOp8XxkotavTCloLDvQmufJPO1L8bnnA+WgP2YgVZ 5MJTj/t4DI+yQgysEjsH8aurHO2uuqgJE+xK+2dy6Cl/wskuGxObksSPmmFH5PH0Joziwrtl 61ouLE2XwKbkMgIGEKkbFgbfwz3/QuLZGBni+OOtLzXeZ9wNTW/AHUPy6S9U4F+5z6/09fVT tTH0cvrgAGjbASlYx2VqGONXAsxCfjulq6ryJBFlPLp949c/JTTgOojukCSbABEBAAHCwHYE GAEIACACGwwWIQQtG9pGQ7sz3tf8M/kC7fV9o/vRzgUCZL1H0gAKCRAC7fV9o/vRzlamCACs vHw+0heTm+BfC3S8DUST6889gidIIwdqBep1ByzetCph7Bq8Y8BlT5YTX0u/bSKkxCzFgeTm vC341Q09ST2XjLAl1ZTdzGhH9gcgYyOw34pr5fPQRJLB392mPzD8YReRzciNbhWzj+DLgeVe ouyfGajd6jDjkf4FEq+trQLGZhpfsKn3JnDbzBUs945D50l/vz9q/QN3qZO+H4F6g8ZeMnqo FOEFN26xVtdEDr+0DNFsbgKmEzs675kdAY78ZZdbEetX/FSknxJ+FK1ZW3J7Yswwulj34AXP LB49Mk8Ot7fo6mdt0DkV11JS9LmKxKvpY+KTlrKG+i7pVCSZvVUx In-Reply-To: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/20/26 05:36, Gary Bisson wrote: > Some bridges, such as the TI SN65DSI83, require the HS clock to be > running in order to lock its PLL during its own pre-enable function. > > Without this change, the bridge gives the following error: > sn65dsi83 14-002c: failed to lock PLL, ret=-110 > sn65dsi83 14-002c: Unexpected link status 0x01 > sn65dsi83 14-002c: reset the pipe > > Move the necessary functions from enable to pre-enable. > > Signed-off-by: Gary Bisson > --- > Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel. > > Left mtk_dsi_set_mode() as part of the enable function to mimic what is > done in the Samsung DSIM driver which is known to be working the TI > bridge. > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++------------------ > 1 file changed, 17 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 0e2bcd5f67b7..b560245d1be9 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) > } > } > > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > +{ > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + usleep_range(1000, 3000); > + /* The reaction time after pulling up the mipi signal for dsi_rx */ > + } > +} > + > static int mtk_dsi_poweron(struct mtk_dsi *dsi) > { > struct device *dev = dsi->host.dev; > @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > + mtk_dsi_lane_ready(dsi); > + mtk_dsi_clk_hs_mode(dsi, 1); > > return 0; > err_disable_engine_clk: > @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > dsi->lanes_ready = false; > } > > -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > -{ > - if (!dsi->lanes_ready) { > - dsi->lanes_ready = true; > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - usleep_range(1000, 3000); > - /* The reaction time after pulling up the mipi signal for dsi_rx */ > - } > -} > - > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > { > if (dsi->enabled) > return; > > - mtk_dsi_lane_ready(dsi); > mtk_dsi_set_mode(dsi); > - mtk_dsi_clk_hs_mode(dsi, 1); > - > mtk_dsi_start(dsi); > > dsi->enabled = true; > > --- > base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 > change-id: 20260120-mtkdsi-29e4c84e7b38 > > Best regards, Hello, This commit was part of 7.1 and caused a problem for me. I'm running postmarketOS (basically Alpine Linux) on a Lenovo C330 chromebook with a Mediatek MT8173 processor. The problem: when the display on my laptop powers off (via suspend or idle, like xset dpms off) the picture does not come back when the display powers back on (from resume). The display backlight comes on and brightness is adjustable but there is no picture. The only fix is to reboot. Reverting this commit and applying it as a patch on top of 7.1 addresses the issue for me. You can view the config I'm using here: https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/8819 Is there any sort of testing or other debugging info I can provide to help address this issue? Thanks, - Adam Thiede