From: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>, wim@linux-watchdog.org
Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org,
linux-kernel@vger.kernel.org, S32@nxp.com,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Thomas Fossati <thomas.fossati@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer
Date: Mon, 31 Mar 2025 13:55:45 +0300 [thread overview]
Message-ID: <4267a636-d858-55f0-01fe-c5d7265ed3c6@oss.nxp.com> (raw)
In-Reply-To: <20250328151516.2219971-1-daniel.lezcano@linaro.org>
On 3/28/2025 5:15 PM, Daniel Lezcano wrote:
> Describe the Software Watchdog Timer available on the S32G platforms.
>
> Cc: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> Cc: Thomas Fossati <thomas.fossati@linaro.org>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> .../bindings/watchdog/nxp,s32g-wdt.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
>
> diff --git a/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
> new file mode 100644
> index 000000000000..06ead743d5c1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/watchdog/nxp,s32g-wdt.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP Software Watchdog Timer
> +
> +maintainers:
> + - Daniel Lezcano <daniel.lezcano@kernel.org>
> +
> +description:
> + The System Timer Module supports commonly required system and
> + application software timing functions. STM includes a 32-bit
> + count-up timer and four 32-bit compare channels with a separate
> + interrupt source for each channel. The timer is driven by the STM
> +
Please update the description, as this one refers to STM instead of SWT.
--
Regards,
Ghennadi
prev parent reply other threads:[~2025-03-31 10:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-28 15:15 Daniel Lezcano
2025-03-28 15:15 ` [PATCH 2/2] watchdog: Add the Software Watchdog Timer for the NXP S32 platform Daniel Lezcano
2025-03-28 18:10 ` Guenter Roeck
2025-03-28 19:42 ` Daniel Lezcano
2025-03-28 19:56 ` Guenter Roeck
2025-03-28 20:58 ` Daniel Lezcano
2025-03-29 4:55 ` Krzysztof Kozlowski
2025-03-31 8:28 ` Daniel Lezcano
2025-03-29 1:37 ` [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer Rob Herring (Arm)
2025-03-29 17:12 ` Rob Herring
2025-03-31 8:18 ` Daniel Lezcano
2025-03-29 5:04 ` Krzysztof Kozlowski
2025-03-31 7:57 ` Daniel Lezcano
2025-03-31 11:42 ` Krzysztof Kozlowski
2025-04-01 8:46 ` Daniel Lezcano
2025-04-01 15:16 ` Krzysztof Kozlowski
2025-03-31 10:55 ` Ghennadi Procopciuc [this message]
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