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Wed, 04 Nov 2026 14:44:34 -0800 (PST) Received: from [192.168.0.167] ([109.76.163.117]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48fed551dbasm6028154f8f.37.2026.11.04.14.44.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Nov 2026 14:44:33 -0800 (PST) Message-ID: <427eb0e0-5e10-4f24-8686-4d06c26cdd13@linaro.org> Date: Wed, 4 Nov 2026 22:44:31 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: media: qcom,sm8150-camss: Add SM8150 CAMSS To: mail@andrewgigena.dev, Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20261104-sm8150-v7-4-rc1-camss-v1-0-7a9534a9a22f@andrewgigena.dev> <20261104-sm8150-v7-4-rc1-camss-v1-2-7a9534a9a22f@andrewgigena.dev> From: Bryan O'Donoghue Content-Language: en-GB In-Reply-To: <20261104-sm8150-v7-4-rc1-camss-v1-2-7a9534a9a22f@andrewgigena.dev> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/11/2026 20:54, Andrew Gigena via B4 Relay wrote: > From: Andrew Gigena > > Document the Qualcomm SM8150 Camera Subsystem. The IP integrates four > CSIPHY, four CSID (two full and two lite), two VFE and two VFE-Lite > instances, with 42 clocks, 12 interrupts, eight IOMMU streams, four > interconnect paths and three power domains. > > SM8150 has a different register layout, clock tree and power domain > topology from SM8250, so describe it in a dedicated schema instead of > using qcom,sm8250-camss as a fallback. > > Signed-off-by: Andrew Gigena > --- > .../bindings/media/qcom,sm8150-camss.yaml | 477 +++++++++++++++++++++ > 1 file changed, 477 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml > new file mode 100644 > index 000000000000..a65067352b58 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml > @@ -0,0 +1,477 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8150-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8150 Camera Subsystem (CAMSS) > + > +maintainers: > + - Andrew Gigena > + > +description: | > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8150-camss > + > + clocks: > + minItems: 42 > + maxItems: 42 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: camnoc_axi_src > + - const: cpas_ahb > + - const: cphy_rx_src > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy0_timer_src > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy1_timer_src > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy2_timer_src > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy3_timer_src > + - const: vfe0_axi > + - const: vfe0 > + - const: vfe0_src > + - const: vfe0_cphy_rx > + - const: vfe0_csid > + - const: vfe0_csid_src > + - const: vfe1_axi > + - const: vfe1 > + - const: vfe1_src > + - const: vfe1_cphy_rx > + - const: vfe1_csid > + - const: vfe1_csid_src > + - const: vfe_lite0 > + - const: vfe_lite0_src > + - const: vfe_lite0_cphy_rx > + - const: vfe_lite0_csid > + - const: vfe_lite0_csid_src > + - const: vfe_lite1 > + - const: vfe_lite1_src > + - const: vfe_lite1_cphy_rx > + - const: vfe_lite1_csid > + - const: vfe_lite1_csid_src > + - const: slow_ahb_src > + - const: gcc_ahb > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + > + interrupts: > + minItems: 12 > + maxItems: 12 > + > + interrupt-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: vfe0 > + - const: csid0 > + - const: vfe1 > + - const: csid1 > + - const: vfe_lite0 > + - const: csid_lite0 > + - const: vfe_lite1 > + - const: csid_lite1 > + > + iommus: > + maxItems: 8 > + > + interconnects: > + maxItems: 4 > + > + interconnect-names: > + items: > + - const: cam_ahb > + - const: cam_hf_0_mnoc > + - const: cam_hf_1_mnoc > + - const: cam_sf_0_mnoc > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data from CSIPHY0. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data from CSIPHY1. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data from CSIPHY2. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data from CSIPHY3. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + reg: > + minItems: 12 > + maxItems: 12 > + > + reg-names: > + items: > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: vfe0 > + - const: csid0 > + - const: vfe1 > + - const: csid1 > + - const: vfe_lite0 > + - const: csid_lite0 > + - const: vfe_lite1 > + - const: csid_lite1 > + > + vdda-phy-supply: > + description: > + Phandle to a regulator supply to PHY core block. > + > + vdda-pll-supply: > + description: > + Phandle to 1.8V regulator supply to PHY refclk pll block. > + > +required: > + - clock-names > + - clocks > + - compatible > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domain-names > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@ac65000 { > + compatible = "qcom,sm8150-camss"; > + > + reg = <0 0xac65000 0 0x1000>, > + <0 0xac66000 0 0x1000>, > + <0 0xac67000 0 0x1000>, > + <0 0xac68000 0 0x1000>, > + <0 0xacaf000 0 0x4000>, > + <0 0xacb3000 0 0x1000>, > + <0 0xacb6000 0 0x4000>, > + <0 0xacba000 0 0x1000>, > + <0 0xacc4000 0 0x4000>, > + <0 0xacc8000 0 0x1000>, > + <0 0xaccb000 0 0x4000>, > + <0 0xaccf000 0 0x1000>; > + > + reg-names = "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "vfe0", > + "csid0", > + "vfe1", > + "csid1", > + "vfe_lite0", > + "csid_lite0", > + "vfe_lite1", > + "csid_lite1"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names = "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "vfe0", > + "csid0", > + "vfe1", > + "csid1", > + "vfe_lite0", > + "csid_lite0", > + "vfe_lite1", > + "csid_lite1"; > + > + power-domains = <&camcc IFE_0_GDSC>, > + <&camcc IFE_1_GDSC>, > + <&camcc TITAN_TOP_GDSC>; > + > + power-domain-names = "ife0", > + "ife1", > + "top"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, > + <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, > + <&camcc CAM_CC_IFE_0_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_CLK_SRC>, > + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, > + <&camcc CAM_CC_IFE_1_AXI_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_CLK_SRC>, > + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_1_CSID_CLK>, > + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, > + <&camcc CAM_CC_IFE_LITE_0_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CLK_SRC>, > + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>, > + <&camcc CAM_CC_IFE_LITE_1_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CLK_SRC>, > + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>; > + > + clock-names = "camnoc_axi", > + "camnoc_axi_src", > + "cpas_ahb", > + "cphy_rx_src", > + "csiphy0", > + "csiphy0_timer", > + "csiphy0_timer_src", > + "csiphy1", > + "csiphy1_timer", > + "csiphy1_timer_src", > + "csiphy2", > + "csiphy2_timer", > + "csiphy2_timer_src", > + "csiphy3", > + "csiphy3_timer", > + "csiphy3_timer_src", > + "vfe0_axi", > + "vfe0", > + "vfe0_src", > + "vfe0_cphy_rx", > + "vfe0_csid", > + "vfe0_csid_src", > + "vfe1_axi", > + "vfe1", > + "vfe1_src", > + "vfe1_cphy_rx", > + "vfe1_csid", > + "vfe1_csid_src", > + "vfe_lite0", > + "vfe_lite0_src", > + "vfe_lite0_cphy_rx", > + "vfe_lite0_csid", > + "vfe_lite0_csid_src", > + "vfe_lite1", > + "vfe_lite1_src", > + "vfe_lite1_cphy_rx", > + "vfe_lite1_csid", > + "vfe_lite1_csid_src", > + "slow_ahb_src", > + "gcc_ahb", > + "gcc_axi_hf", > + "gcc_axi_sf"; 42 is ofc a sacred number so its a pity BUT you almost certainly don't need the _src clocks here. > + > + iommus = <&apps_smmu 0x840 0x620>, > + <&apps_smmu 0x860 0x620>, > + <&apps_smmu 0xA40 0x620>, > + <&apps_smmu 0xA60 0x620>, > + <&apps_smmu 0xC40 0x620>, > + <&apps_smmu 0xC60 0x620>, > + <&apps_smmu 0xE40 0x620>, > + <&apps_smmu 0xE60 0x620>; > + > + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF0 0 &mc_virt SLAVE_EBI_CH0 0>, > + <&mmss_noc MASTER_CAMNOC_HF1 0 &mc_virt SLAVE_EBI_CH0 0>, > + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>; > + > + interconnect-names = "cam_ahb", > + "cam_hf_0_mnoc", > + "cam_hf_1_mnoc", > + "cam_sf_0_mnoc"; > + > + vdda-phy-supply = <&vreg_l5a_0p88>; > + vdda-pll-supply = <&vreg_l3c_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy_ep0: endpoint@0 { > + reg = <0>; > + clock-lanes = <7>; > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&sensor_ep>; > + }; > + }; > + }; > + }; > + }; >