From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752110AbbIOM27 (ORCPT ); Tue, 15 Sep 2015 08:28:59 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:38113 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751852AbbIOM2u (ORCPT ); Tue, 15 Sep 2015 08:28:50 -0400 X-AuditID: cbfee61b-f79d56d0000048c5-63-55f80effc4e0 From: Bartlomiej Zolnierkiewicz To: Michael Turquette Cc: Thomas Abraham , Sylwester Nawrocki , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Dan Carpenter , Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stephen Boyd Subject: Re: [PATCH v2] clk: samsung: fix cpu clock's flags checking Date: Tue, 15 Sep 2015 14:28:39 +0200 Message-id: <4294976.g7Mb9GifR6@amdc1976> User-Agent: KMail/4.13.3 (Linux/3.13.0-63-generic; KDE/4.13.3; x86_64; ; ) In-reply-to: <1440762575-21520-1-git-send-email-b.zolnierkie@samsung.com> References: <1440762575-21520-1-git-send-email-b.zolnierkie@samsung.com> MIME-version: 1.0 Content-transfer-encoding: 7Bit Content-type: text/plain; charset=us-ascii X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQd3/fD9CDZbvMLC4/uU5q8Xrf9NZ LP4/es1qce33DDaL1y8MLXoXXGWz6H/8mtni6+EVjBZvHm5mtNj0+Bqrxceee6wWl3fNYbP4 3HuE0WLG+X1MFhdPuVocftPOavHjTDeLRccyRotVu/4wWmz86uEg4vH+Riu7x+W+XiaPv7Nb mT12zrrL7rFpVSebx51re9g8Ni+p9/j49BaLR9+WVYwe26/NY/b4vEkugDuKyyYlNSezLLVI 3y6BK+P++TXMBZ+kK77vmMzWwNgo3sXIySEhYCLR8vUpG4QtJnHh3nogm4tDSGAWo8SGL9ug nK+MEqe/H2UGqWITsJKY2L6KEcQWEdCXaHrwD6yIWeAOq0TnsY3sIAlhAReJb89/gzWwCKhK HL9wDczmFdCU2NDeyQRiiwp4Sbz/ORcszingKfFy4x4WEFtIwEOibcckVoh6QYkfk++BxZkF 5CX27Z/KCmFrSazfeZxpAiPQnQhls5CUzUJStoCReRWjRGpBckFxUnquUV5quV5xYm5xaV66 XnJ+7iZGcIw+k97BeHiX+yFGAQ5GJR7eiPbvoUKsiWXFlbmHGCU4mJVEeGU5foQK8aYkVlal FuXHF5XmpBYfYpTmYFES55Vd+SxUSCA9sSQ1OzW1ILUIJsvEwSnVwBjkzc+80101oXZVmqxn c/W0PbqXlNb2+094sv7GhykGJ+SdpRL8Vk/cx5KXl2q7Ztr1LfsX/pO/U+/8/Ley/4x3C88/ bfxldsDLeonJCrEu9dJr98q0HH/xxpku3RU96fJlEcvPzRNm1DM5nSg+FsZt09oZ9P725wwX T9OEQ3wMbVza5w56/VViKc5INNRiLipOBABmwfnvzQIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [ + Stephen on cc: ] On Friday, August 28, 2015 01:49:35 PM Bartlomiej Zolnierkiewicz wrote: > CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were > incorrectly used as a bit numbers. Fix it. > > Tested on Exynos4210 based Origen board and on Exynos5250 based > Arndale board. > > Cc: Tomasz Figa > Cc: Michael Turquette > Cc: Thomas Abraham > Fixes: ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks") > Reported-by: Dan Carpenter > Reviewed-by: Krzysztof Kozlowski > Reviewed-by: Javier Martinez Canillas > Acked-by: Sylwester Nawrocki > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > v2: > - added Reviewed-by, Acked-by and Fixes tags (no code changes) > > Michael, please apply. Thank you. Gentle ping. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics > drivers/clk/samsung/clk-cpu.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c > index 7c1e1f5..2fe37f7 100644 > --- a/drivers/clk/samsung/clk-cpu.c > +++ b/drivers/clk/samsung/clk-cpu.c > @@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, > * the values for DIV_COPY and DIV_HPM dividers need not be set. > */ > div0 = cfg_data->div0; > - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) { > + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { > div1 = cfg_data->div1; > if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) > div1 = readl(base + E4210_DIV_CPU1) & > @@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, > alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; > WARN_ON(alt_div >= MAX_DIV); > > - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { > + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { > /* > * In Exynos4210, ATB clock parent is also mout_core. So > * ATB clock also needs to be mantained at safe speed. > @@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, > writel(div0, base + E4210_DIV_CPU0); > wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL); > > - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) { > + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { > writel(div1, base + E4210_DIV_CPU1); > wait_until_divider_stable(base + E4210_DIV_STAT_CPU1, > DIV_MASK_ALL); > @@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, > unsigned long mux_reg; > > /* find out the divider values to use for clock data */ > - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { > + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { > while ((cfg_data->prate * 1000) != ndata->new_rate) { > if (cfg_data->prate == 0) > return -EINVAL; > @@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, > writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); > wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1); > > - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { > + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { > div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); > div_mask |= E4210_DIV0_ATB_MASK; > }