From: Eric Dumazet <dada1@cosmosbay.com>
To: Andi Kleen <ak@suse.de>
Cc: linux-kernel@vger.kernel.org
Subject: [PATCH] x86_64 prefetchw() function can take into account CONFIG_MK8 / CONFIG_MPSC
Date: Thu, 23 Jun 2005 11:32:34 +0200 [thread overview]
Message-ID: <42BA81B2.4070108@cosmosbay.com> (raw)
In-Reply-To: <20050622231300.GC14251@wotan.suse.de>
[-- Attachment #1: Type: text/plain, Size: 155 bytes --]
If we build a x86_64 kernel for an AMD64 or for an Intel EMT64, no need to use alternative_input.
Reserve alternative_input only for a generic kernel.
[-- Attachment #2: patch.2 --]
[-- Type: text/plain, Size: 1075 bytes --]
diff -Nru linux-2.6.12/include/asm-x86_64/processor.h linux-2.6.12-orig/include/asm-x86_64/processor.h
--- linux-2.6.12-orig/include/asm-x86_64/processor.h 2005-06-17 21:48:29.000000000 +0200
+++ linux-2.6.12/include/asm-x86_64/processor.h 2005-06-23 11:20:08.000000000 +0200
@@ -389,10 +389,21 @@
#define ARCH_HAS_PREFETCHW 1
static inline void prefetchw(void *x)
{
+#if defined(CONFIG_MK8)
+ /* AMD64 / MK8 has 3DNOW, we can emit a true prefetchw, using a "m" in the asm input */
+ asm volatile("prefetchw %0" :: "m" (*(unsigned long *)x));
+#elif defined(CONFIG_MPSC)
+ /* Intel EMT64 does not have 3DNOW, no prefetchw instruction */
+#else
+ /* If we build a generic X86_64 kernel,
+ * we must use alternative_input() and a "r" asm constraint to make sure
+ * the size of the instruction will be <= 5
+ */
alternative_input(ASM_NOP5,
"prefetchw (%1)",
X86_FEATURE_3DNOW,
"r" (x));
+#endif
}
#define ARCH_HAS_SPINLOCK_PREFETCH 1
next parent reply other threads:[~2005-06-23 9:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20050622.132241.21929037.davem@davemloft.net>
[not found] ` <200506222242.j5MMgbxS009935@guinness.s2io.com>
[not found] ` <20050622231300.GC14251@wotan.suse.de>
2005-06-23 9:32 ` Eric Dumazet [this message]
2005-06-23 9:37 ` Eric Dumazet
2005-06-23 11:31 ` Andi Kleen
2005-06-23 12:53 ` Eric Dumazet
2005-06-23 13:10 ` Andi Kleen
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