From: Carolina Jubran <cjubran@nvidia.com>
To: netdev-bot+sinfo@kernel.org, Tariq Toukan <tariqt@nvidia.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>,
netdev@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Gal Pressman <gal@nvidia.com>, Jiri Pirko <jiri@nvidia.com>,
Jiri Pirko <jiri@resnulli.us>, Leon Romanovsky <leon@kernel.org>,
open list <linux-kernel@vger.kernel.org>,
linux-rdma@vger.kernel.org, Mark Bloch <mbloch@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>
Subject: Re: [PATCH net] net/mlx5: DPLL, fix fractional frequency offset scaling
Date: Thu, 15 Oct 2026 12:28:28 +0300 [thread overview]
Message-ID: <42a510da-caf1-4847-b938-1cebeacd3880@nvidia.com> (raw)
In-Reply-To: <179205022689.408196.2502809558369367458@kernel.org>
On 15/10/2026 10:43, netdev-bot+sinfo@kernel.org wrote:
> Hi!
>
> This is an automated message. This series looks like a fix, but its
> commit messages seem to be missing some information:
>
> - How the issue was discovered, e.g. hit in production, hit during
> development, syzbot report, manual code inspection, LLM or static
> analysis tool scan.
>
> - Whether the issue was actually triggered, or is only theoretical
> (e.g. found by code inspection). If it was triggered please include
> the symptoms, like the stack trace or error messages.
>
> - What hardware the change was tested on. For driver fixes please
> mention the device (and if relevant firmware version) used for
> testing, or say that the change was not tested on real hardware.
>
> Please do not repost the series just to address the above. Instead,
> reply to this email with the missing information, so that reviewers
> can take it into account. If the series needs another revision for
> other reasons, please include the information in the commit messages
> then.
>
> The evaluation is done by an LLM so it may be wrong, if you think
> that is the case please reply and explain.
Hi,
The issue was found while testing the latest mlx5 driver on an older
kernel that does not support
DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT.
There was no crash or kernel warning. Just that the legacy
DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET attribute reported an incorrect
FFO value.
The mlx5 firmware reports frequency_diff in ppt. Although the legacy
attribute is documented in ppm, our userspace application has always
expected the value exported by mlx5 to be in ppt.
On newer kernels, the driver multiplies the firmware value by 1,000,000
to account for the corresponding division performed by the DPLL core
when exporting the legacy attribute. Older kernels do not perform this
division and expose the scaled value directly, resulting in an FFO value
1,000,000 times too large.
The change was tested on CX6Dx, and the reported FFO value was verified
through both the DPLL netlink interface and our userspace application.
Thanks,
Carolina
next prev parent reply other threads:[~2026-10-15 9:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-15 7:40 Tariq Toukan
2026-10-15 7:43 ` netdev-bot+sinfo
2026-10-15 9:28 ` Carolina Jubran [this message]
2026-10-15 10:49 ` Daniel Machon
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