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Mon, 03 Mar 2025 00:28:49 -0800 (PST) Message-ID: <430f1dae-0123-4d4a-81c9-b3c1d9df285d@tuxon.dev> Date: Mon, 3 Mar 2025 10:28:47 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 17/21] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC To: Ryan.Wanner@microchip.com, lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, sre@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, p.zabel@pengutronix.de Cc: linux@armlinux.org.uk, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org References: <6a1c058edee3fe1459dcb3a93a0a789a9ffff5f3.1740671156.git.Ryan.Wanner@microchip.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <6a1c058edee3fe1459dcb3a93a0a789a9ffff5f3.1740671156.git.Ryan.Wanner@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Ryan, On 27.02.2025 17:52, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner > > Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able > to store the RTT time data. > > Signed-off-by: Ryan Wanner > --- > arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi > index b0a676623100..aadeea132289 100644 > --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi > +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi > @@ -120,6 +120,13 @@ shdwc: poweroff@e001d200 { > status = "disabled"; > }; > > + rtt: rtc@e001d300 { > + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; > + reg = <0xe001d300 0x30>; > + interrupts = ; > + clocks = <&clk32k 0>; > + }; > + > clk32k: clock-controller@e001d500 { > compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; > reg = <0xe001d500 0x4>; > @@ -132,6 +139,11 @@ chipid@e0020000 { > reg = <0xe0020000 0x8>; > }; > > + gpbr: gpbr@e001d700 { > + compatible = "microchip,sama7d65-gpbr", "syscon"; This is not documented. I'll postpone this until a documentation patch will be posted. > + reg = <0xe001d700 0x48>; > + }; > + > dma2: dma-controller@e1200000 { > compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; > reg = <0xe1200000 0x1000>;