From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51004E81E10 for ; Fri, 6 Oct 2023 15:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232851AbjJFPnF (ORCPT ); Fri, 6 Oct 2023 11:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232152AbjJFPnE (ORCPT ); Fri, 6 Oct 2023 11:43:04 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 035A69E for ; Fri, 6 Oct 2023 08:43:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696606984; x=1728142984; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=fQsFBquArgc+9IJQ4xqInI1mZINN33gx7S35zWcm+b8=; b=BvrhtbOKpAMCiVsBo1jgito6EUirFAFARxx7daZeum36kPPqbD0ZRv92 NREv97BJab6X/adCAV7HfyLvQJPKzWd0niYMPG7T6rzDpjcDSZd7aJrUO POtzEabiKdnk0io7r3eiL5X/hNfWBfjAu6/mK4iDk4j6e0m3ANM3CIcp1 2TikUHhLK8EmogZOJmGA5NFpIIqVy6jXjb0Kw0kI1Col0tfjQl+EG5WGX aPj+YfgxfjmKQgW+c40db/roEzNbWgjh4MbWtrrb4QyyOt6l/B5ELFG4T DVom9/GI+Va+KfJwQdIhy7JImmNblzfWsXjJnE9G3YR7xecRfSrjdPuj7 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="368849745" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="368849745" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 08:43:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="1083491800" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="1083491800" Received: from dhimanbh-mobl1.amr.corp.intel.com (HELO [10.209.88.92]) ([10.209.88.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 08:43:02 -0700 Message-ID: <4325732d-f5cc-b15b-157b-e5b0e61f8976@intel.com> Date: Fri, 6 Oct 2023 08:43:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] x86/tdx: Override the tsc calibration for TDX VMs Content-Language: en-US To: Vishal Annapurve Cc: "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Jun Nakajima , Isaku Yamahata , Erdem Aktas , Sagi Shahar , Sean Christopherson , Nikolay Borisov , "Jason A. Donenfeld" , Kuppuswamy Sathyanarayanan , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org References: <20231006011255.4163884-1-vannapurve@google.com> <2d952c6b-2357-208b-e816-bca19c2a7ca6@intel.com> From: Dave Hansen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/6/23 08:27, Vishal Annapurve wrote: >> Would it be possible to do this by refactoring the existing code and >> calling it directly instead of copying and pasting so much? > One option is to call native_calibrate_tsc from tdx_calibrate_tsc and > undo the lapic_timer_period configuration after the call. Does that > sound reasonable? That sounds like a hack. Why not just refactor the code properly?