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From: Len Brown <lenb@kernel.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, Len Brown <len.brown@intel.com>
Subject: [PATCH 7/9] x86 tsc_msr: Remove irqoff around MSR-based TSC enumeration
Date: Thu, 31 Mar 2016 00:13:53 -0400	[thread overview]
Message-ID: <433f82c8ab3fcaa7ff3b852d01cc74dbdf6d94f1.1459397558.git.len.brown@intel.com> (raw)
In-Reply-To: <1459397635-4871-1-git-send-email-lenb@kernel.org>
In-Reply-To: <6e0c25e64e0fb65a42dfc63ad5f660302e07cd87.1459397558.git.len.brown@intel.com>

From: Len Brown <len.brown@intel.com>

Remove the irqoff/irqon around MSR-based TSC enumeration,
as it is not necessary.

Also rename: try_msr_calibrate_tsc() to cpu_khz_from_msr(),
as that better describes what the routine does.

Signed-off-by: Len Brown <len.brown@intel.com>
---
 arch/x86/include/asm/tsc.h | 3 +--
 arch/x86/kernel/tsc.c      | 5 +----
 arch/x86/kernel/tsc_msr.c  | 2 +-
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 174c421..d634f2a 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -52,7 +52,6 @@ extern int notsc_setup(char *);
 extern void tsc_save_sched_clock_state(void);
 extern void tsc_restore_sched_clock_state(void);
 
-/* MSR based TSC calibration for Intel Atom SoC platforms */
-unsigned long try_msr_calibrate_tsc(void);
+unsigned long cpu_khz_from_msr(void);
 
 #endif /* _ASM_X86_TSC_H */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index c9c4c7c..0ffb57f 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -674,10 +674,7 @@ unsigned long native_calibrate_tsc(void)
 	unsigned long flags, latch, ms, fast_calibrate;
 	int hpet = is_hpet_enabled(), i, loopmin;
 
-	/* Calibrate TSC using MSR for Intel Atom SoCs */
-	local_irq_save(flags);
-	fast_calibrate = try_msr_calibrate_tsc();
-	local_irq_restore(flags);
+	fast_calibrate = cpu_khz_from_msr();
 	if (fast_calibrate)
 		return fast_calibrate;
 
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index c8ea977..b0839c5 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -68,7 +68,7 @@ static int match_cpu(u8 family, u8 model)
  * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
  * Return processor base frequency in KHz, or 0 on failure.
  */
-unsigned long try_msr_calibrate_tsc(void)
+unsigned long cpu_khz_from_msr(void)
 {
 	u32 lo, hi, ratio, freq_id, freq;
 	unsigned long res;
-- 
2.8.0.rc4.16.g56331f8

  parent reply	other threads:[~2016-03-31  4:15 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-31  4:13 [PATCH 0/9] x86: TSC calibration update Len Brown
2016-03-31  4:13 ` [PATCH 1/9] x86 tsc_msr: Identify Intel-specific code Len Brown
2016-03-31  4:13   ` [PATCH 2/9] x86 tsc_msr: Remove debugging messages Len Brown
2016-03-31  4:13   ` [PATCH 3/9] x86 tsc_msr: Update comments, expand definitions Len Brown
2016-03-31  4:13   ` [PATCH 4/9] x86 tsc_msr: Correct Silvermont reference clock values Len Brown
2016-03-31  4:13   ` [PATCH 5/9] x86 tsc_msr: Add Airmont " Len Brown
2016-03-31  4:13   ` [PATCH 6/9] x86 tsc_msr: Extend to include Intel Core Architecture Len Brown
2016-03-31  4:13   ` Len Brown [this message]
2016-03-31  4:13   ` [PATCH 8/9] x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID Len Brown
2016-03-31  4:13   ` [PATCH 9/9] x86 tsc: enumerate BXT " Len Brown
2016-06-10 13:20 ` [PATCH 0/9] x86: TSC calibration update Thomas Gleixner

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