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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66e02f389absm4833458a12.13.2026.04.08.02.57.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 02:57:20 -0700 (PDT) Message-ID: <4359bb07-d848-4b77-b1a9-f1c6f53caa10@oss.qualcomm.com> Date: Wed, 8 Apr 2026 11:57:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support To: jsandom@axon.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com> <20260407-rb5gen2-dts-v2-5-d0c7f447ee73@axon.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260407-rb5gen2-dts-v2-5-d0c7f447ee73@axon.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: AG0XJD86eSYqGcCo6jEki6ZCNqP5fo2V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA4MDA5MCBTYWx0ZWRfXzDc0zWlg4mmv kofw7lZLzynNFwnwjaOoyD7T7kBEk2wZuynoXnzks0C+5fmGPBZkiR/p1sgpkPuh4WEqV2DBiRw qmQ3/UDKwnGUoLhW0r58ZtQ6gWVtAAjaaFHEHTpnmKvs8qiNY2xYnaYFtKA/+Xz96FFNTG+Xvgn BGICcUtzS0/ccF1zYrmbQSD+ISHZJ+kEtnGItDQpEmxr2fMJ+t0ntQ+yuJNBoDl4cBuTehTf12y 89Fxsu9p08zUeTUuHQdm+XPW/Qdv4Ny6rKQUXk66eDDpNlGXPqMjXII4pbhM9ZgBIBod3jnxOF4 CzXBRo5NDig5EkjLKngBTYYs0RMgEHMcjR6mDlVoGor2XzdVPGQ9Z5J3C0u6GN9+hfdFd2+yKZH O+fJHe2lzb7Nqp6Bhv5liMdUm+3b7EUcvp18j8LqCW4ZRdDyTljnc0eLy9YvSgLlGebv7g3dtuz D0nm7usH0lRdeItjozA== X-Proofpoint-ORIG-GUID: AG0XJD86eSYqGcCo6jEki6ZCNqP5fo2V X-Authority-Analysis: v=2.4 cv=DNS/JSNb c=1 sm=1 tr=0 ts=69d62683 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=h77gEMGJAAAA:8 a=HSvSKgW-rJGLGYoCqIMA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=PYyYjrCoJcZo81GydsRF:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080090 On 4/7/26 5:46 PM, Joe Sandom via B4 Relay wrote: > From: Joe Sandom > > The RB5gen2 is an embedded development platform for the > QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550). [...] > + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */ > + /* Workaround is to use bit-banged I2C */ Interesting.. I was under the impression that it was only an issue on RB1 and RB2 boards.. perhaps we're missing some magic register write.. [...] > + pinctrl-names = "default"; > + pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>, > + <&pmk8550_sleep_clk>; nit: let's keep the order of property-n property-names file-wide [...] > +&sdhc_2 { > + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; > + > + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; > + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; > + pinctrl-names = "default", "sleep"; > + > + vmmc-supply = <&vreg_l9b_2p9>; > + vqmmc-supply = <&vreg_l8b_1p8>; > + > + max-sd-hs-hz = <37000000>; Are you sure you want to overwrite that? The value in the SoC DTSI is set to half a MHz higher > + > + no-sdio; > + no-mmc; > + > + status = "okay"; > +}; > + > +&sleep_clk { > + clock-frequency = <32764>; > +}; > + > +&spi11 { > + status = "okay"; > + > + can@0 { > + compatible = "microchip,mcp2518fd"; > + reg = <0>; > + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk40m>; > + spi-max-frequency = <10000000>; > + vdd-supply = <&vreg_l14b_3p2>; > + xceiver-supply = <&vreg_l14b_3p2>; It may be that for this chip to actually be able to communiate with devices on the bus, you need to set the new 'microchip,xstbyen' property see: https://lore.kernel.org/linux-arm-msm/20260321135031.3107408-1-viken.dadhaniya@oss.qualcomm.com/ [...] > +&tlmm { > + gpio-reserved-ranges = <32 8>; Would you happen to know what these pins are connected to, and if so, add a comment (like in arch/arm64/boot/dts/qcom/x1-crd.dtsi)? > + > + bt_default: bt-default-state { > + pins = "gpio81"; It would be best to keep these entries ordered by pin idx > + function = "gpio"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + sw_ctrl_default: sw-ctrl-default-state { > + pins = "gpio82"; > + function = "gpio"; > + bias-pull-down; > + }; > + > + lt9611_irq_pin: lt9611-irq-state { > + pins = "gpio40"; > + function = "gpio"; > + bias-disable; > + }; > + > + lt9611_rst_pin: lt9611-rst-state { > + pins = "gpio7"; > + function = "gpio"; > + output-high; You shouldn't need to assert the GPIO state in the pin entry node - the driver should take care of that > + }; > + > + ntn0_en: ntn0-en-state { > + pins = "gpio67"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + ntn1_en: ntn1-en-state { > + pins = "gpio42"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + upd_1p05_en: upd-1p05-en-state { > + pins = "gpio179"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; I don't know if pulling up an active-high pin is what you want (there's some more occurences) Konrad