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Tue, 10 Nov 2026 07:28:24 -0800 (PST) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49835c37bdfsm5786450f8f.22.2026.11.10.07.28.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 07:28:23 -0800 (PST) Message-ID: <4371d707-dbe3-4ea4-be1d-c69c38b4012e@linaro.org> Date: Tue, 10 Nov 2026 15:28:22 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes To: Leo Yan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Anshuman Khandual , Tamas Petz , Tamas Zsoldos , Suyash Mahar , Amir Ayupov References: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1@arm.com> <20261016-trbe_enable_disable_irq_handle_refactor-v2-1-3f57cf3199b1@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-1-3f57cf3199b1@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 16/10/2026 17:54, Leo Yan wrote: > TRBSR_EL1.EC identifies the cause of a trace buffer management event, > but the sysreg description does not name its architected values. Define > the five encodings as an unsigned enum so TRBE status handling can > refer to each cause by name. > > The values cover other events, Granule Protection Check faults, > implementation-defined events, and stage 1 and stage 2 Data Aborts on > writes to the trace buffer, as specified by Arm ARM (ARM DDI 0487 M.c). > > Signed-off-by: Leo Yan > --- > arch/arm64/tools/sysreg | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 94bf065c8ac71f20f482c91a5147cb6e001dfba2..f68c23dd4e83ee4d00610e097d9188d3a2c9ed15 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -5834,7 +5834,13 @@ EndSysreg > Sysreg TRBSR_EL1 3 0 9 11 3 > Res0 63:56 > Field 55:32 MSS2 > -Field 31:26 EC > +UnsignedEnum 31:26 EC > + 0b000000 OTHER > + 0b011110 FAULT_GPC > + 0b011111 IMP_DEF > + 0b100100 FAULT_WRITE_S1 > + 0b100101 FAULT_WRITE_S2 > +EndEnum > Res0 25:24 > Field 23 DAT > Field 22 IRQ > Reviewed-by: James Clark