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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8wwYMSFbdc46R9eD+lIlaA+kXMsyqu/7Il6ieIuSFSyS+9UjnvrDwuvMYTdl4WAvHL0PFvqeIITAR/YNlGVrhjFbqXwCwaJotwwbOrK7jjcz0Ve40MuWRiH3us8a9EcVaAQfSwY3Vx5JJkW0w9IaGwu37nHwKhyu7wiBld7ExQqRn7QKOxdauHVCzG+2I9PWg93dFa4BWo2XiYIVWUY1gOuMaxj/Q/MuVfvsK8WT877mk13CQHgbZAQa+YsmqmZn/8RQ70HQ3LLqhyfycJDZ8Nkttx1OgplvjEkAKOrtCPtDH60LpXGx4HFz78+ofeOqLke0itOJ+Dhl0LLyzrGfN51jtrpYKr9RKbr4KKvJn6C76Oxqpu55cTKGtjL+lN0jzYhIoU8NZOYvidTkiarXP0fjTIBKj3X8jk5ygJf275vRkHVEauLPnP/MCsQjOMN8 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2026 10:31:29.8179 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebc96ff5-aaa9-42c2-5c07-08dec7a499a0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B89.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5723 On 6/9/26 18:23, Breno Leitao wrote: > cache_setup_properties() sets use_arch_info = true when DT/ACPI > provide no cache nodes and the arch can derive the topology from > CPU registers (e.g. arm64 reading CLIDR_EL1), but still returns the > original -ENOENT. cache_shared_cpu_map_setup() bails on that error > before the new flag can take effect, so the first CPU brought online > always trips a misleading warning: > > cacheinfo: Unable to detect cache hierarchy for CPU 0 > > Subsequent CPUs skip cache_setup_properties() entirely because > use_arch_info is now true, which is why only CPU0 hits it. This is > reproducible on arm64 with the QEMU 'virt' machine, whose default DT > has no cache nodes. > > Clear ret after setting use_arch_info so the caller proceeds and > populates the shared cpu map via the arch-supplied leaves. > > Fixes: ef9f643a9f8b ("cacheinfo: Add use_arch[|_cache]_info field/function") > Signed-off-by: Breno Leitao > --- > Cc; hruben@meta.com > --- > drivers/base/cacheinfo.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index 70701d3bc81c..4e11d36f127e 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -401,9 +401,18 @@ static int cache_setup_properties(unsigned int cpu) > else if (!acpi_disabled) > ret = cache_setup_acpi(cpu); > > - // Assume there is no cache information available in DT/ACPI from now. > - if (ret && use_arch_cache_info()) > + /* > + * If DT/ACPI lacks cache nodes but the arch can derive the topology > + * from CPU registers (e.g. arm64 reading CLIDR_EL1), fall back to > + * that path instead of propagating the error. Otherwise the very > + * first CPU processed trips a misleading "Unable to detect cache > + * hierarchy" warning, because use_arch_info is only set after the > + * first failure. > + */ NIT: Maybe the comment is a bit long/verbose, but maybe also not worth a v2 Reviewed-by: Pierre Gondois > + if (ret && use_arch_cache_info()) { > use_arch_info = true; > + ret = 0; > + } > > return ret; > } > > --- > base-commit: a87737435cfa134f9cdcc696ba3080759d04cf72 > change-id: 20260609-cacheinfo-b2a8d27a19ce > > Best regards,